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ath9k_hw: fix fast clock handling for 5GHz channels
authorFelix Fietkau <nbd@openwrt.org>
Mon, 26 Apr 2010 19:04:35 +0000 (15:04 -0400)
committerJohn W. Linville <linville@tuxdriver.com>
Tue, 27 Apr 2010 20:09:18 +0000 (16:09 -0400)
Combine multiple checks that were supposed to check for the same
conditions, but didn't. Always enable fast PLL clock on AR9280 2.0

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

No differences found
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