The clock initialization routine sets the DISP* clock parent to PLLC,
resulting in DC failure in the case when PLLD was previously configured.
This issue disrupts chainloading and to prevent failures caused by DISP*
clock parent conflicts, clock initialization should not modify DISP*. The
DC driver handles DISP* configuration.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
- { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },