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+Date: Fri, 8 Jan 2010 21:10:05 +0530\r
+Message-ID: <a8ca84ad1001080740l63fdac79y6b478863b0a5e316@mail.gmail.com>\r
+Subject: [beagleboard] TI:OMAP: [PATCH 3/4] Support 720Mhz configuration for \r
+ OMAP35xx\r
+From: Khasim Syed Mohammed <khasim@beagleboard.org>\r
+To: u-boot@lists.denx.de, beagleboard@googlegroups.com\r
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+Content-Type: multipart/mixed; boundary=001636b2ac6d98250e047ca900e4\r
+\r
+--001636b2ac6d98250e047ca900e4\r
+Content-Type: text/plain; charset=ISO-8859-1\r
+\r
+From bba669562fa208d12f4c7cd8188446e8576cd6ee Mon Sep 17 00:00:00 2001\r
+From: Syed Mohammed Khasim <khasim@ti.com>\r
+Date: Fri, 8 Jan 2010 20:34:37 +0530\r
+Subject: [PATCH] Support 720Mhz configuration for OMAP35xx\r
+\r
+Adds a new API "twl4030_pmrecv_vsel_cfg" to select voltage and group\r
+Adds support for 720Mhz in clock.c\r
+Board file modified to use these new APIs and boot at 720Mhz\r
+\r
+Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>\r
+---\r
+ board/ti/beagle/beagle.c | 20 ++++++++++++++++++--\r
+ cpu/arm_cortexa8/omap3/clock.c | 21 +++++++++++++++++++++\r
+ drivers/power/twl4030.c | 24 +++++++++++++++---------\r
+ include/twl4030.h | 16 ++++++++++++++++\r
+ 4 files changed, 70 insertions(+), 11 deletions(-)\r
+\r
+diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c\r
+index 0def5a6..7985ee9 100644\r
+--- a/board/ti/beagle/beagle.c\r
++++ b/board/ti/beagle/beagle.c\r
+@@ -122,9 +122,27 @@ int misc_init_r(void)\r
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;\r
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;\r
+\r
++ beagle_identify();\r
++\r
+ twl4030_power_init();\r
+ twl4030_led_init();\r
+\r
++ if (beagle_revision == REVISION_C4) {\r
++\r
++ /* Select TWL4030 VSEL to support 720Mhz */\r
++ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,\r
++ VAUX2_VSEL_18,\r
++ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,\r
++ DEV_GRP_P1);\r
++\r
++ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDD1_VSEL,\r
++ VDD1_VSEL_14,\r
++ TWL4030_PM_RECEIVER_VDD1_DEV_GRP,\r
++ DEV_GRP_P1);\r
++\r
++ prcm_config_720mhz();\r
++ }\r
++\r
+ /* Configure GPIOs to output */\r
+ writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);\r
+ writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |\r
+@@ -136,8 +154,6 @@ int misc_init_r(void)\r
+ writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |\r
+ GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);\r
+\r
+- beagle_identify();\r
+-\r
+ dieid_num_r();\r
+\r
+ return 0;\r
+diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c\r
+index 174c453..d67517a 100644\r
+--- a/cpu/arm_cortexa8/omap3/clock.c\r
++++ b/cpu/arm_cortexa8/omap3/clock.c\r
+@@ -402,3 +402,24 @@ void per_clocks_enable(void)\r
+\r
+ sdelay(1000);\r
+ }\r
++\r
++/*\r
++ * Configure PRCM registers to get 720 Mhz\r
++ *\r
++ * NOTE: N value doesn't change, only M gets affected\r
++ */\r
++void prcm_config_720mhz(void)\r
++{\r
++ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;\r
++\r
++ /* Unlock MPU DPLL (slows things down, and needed later) */\r
++ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);\r
++ wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);\r
++\r
++ /* Set M */\r
++ sr32(&prcm_base->clksel1_pll_mpu, 8, 11, 0x2D0);\r
++\r
++ /* lock mode */\r
++ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);\r
++ wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);\r
++}\r
+diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c\r
+index eb066cb..d68e515 100644\r
+--- a/drivers/power/twl4030.c\r
++++ b/drivers/power/twl4030.c\r
+@@ -59,16 +59,9 @@ void twl4030_power_reset_init(void)\r
+ }\r
+ }\r
+\r
+-\r
+ /*\r
+ * Power Init\r
+ */\r
+-#define DEV_GRP_P1 0x20\r
+-#define VAUX3_VSEL_28 0x03\r
+-#define DEV_GRP_ALL 0xE0\r
+-#define VPLL2_VSEL_18 0x05\r
+-#define VDAC_VSEL_18 0x03\r
+-\r
+ void twl4030_power_init(void)\r
+ {\r
+ unsigned char byte;\r
+@@ -98,8 +91,6 @@ void twl4030_power_init(void)\r
+ TWL4030_PM_RECEIVER_VDAC_DEDICATED);\r
+ }\r
+\r
+-#define VMMC1_VSEL_30 0x02\r
+-\r
+ void twl4030_power_mmc_init(void)\r
+ {\r
+ unsigned char byte;\r
+@@ -113,3 +104,18 @@ void twl4030_power_mmc_init(void)\r
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,\r
+ TWL4030_PM_RECEIVER_VMMC1_DEDICATED);\r
+ }\r
++\r
++/*\r
++ * Generic function to select Device Group and Voltage\r
++ */\r
++void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,\r
++ u8 dev_grp, u8 dev_grp_sel)\r
++{\r
++ /* Select the Device Group */\r
++ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,\r
++ dev_grp);\r
++\r
++ /* Select the Voltage */\r
++ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,\r
++ vsel_reg);\r
++}\r
+diff --git a/include/twl4030.h b/include/twl4030.h\r
+index f260ecb..b96c96c 100644\r
+--- a/include/twl4030.h\r
++++ b/include/twl4030.h\r
+@@ -359,6 +359,22 @@\r
+ #define TWL4030_USB_PHY_DPLL_CLK (1 << 0)\r
+\r
+ /*\r
++ * Voltage Selection in PM Receiver Module\r
++ */\r
++#define VAUX2_VSEL_18 0x05\r
++#define VDD1_VSEL_14 0x40\r
++#define VAUX3_VSEL_28 0x03\r
++#define VPLL2_VSEL_18 0x05\r
++#define VDAC_VSEL_18 0x03\r
++#define VMMC1_VSEL_30 0x02\r
++\r
++/*\r
++ * Device Selection\r
++ */\r
++#define DEV_GRP_P1 0x20\r
++#define DEV_GRP_ALL 0xE0\r
++\r
++/*\r
+ * Convience functions to read and write from TWL4030\r
+ *\r
+ * chip_no is the i2c address, it must be one of the chip addresses\r
+-- \r
+1.5.6.3\r
+\r
+--001636b2ac6d98250e047ca900e4\r
+Content-Type: text/plain; charset=ISO-8859-1\r
+\r
+-- \r
+You received this message because you are subscribed to the Google Groups "Beagle Board" group.\r
+To post to this group, send email to beagleboard@googlegroups.com.\r
+To unsubscribe from this group, send email to beagleboard+unsubscribe@googlegroups.com.\r
+For more options, visit this group at http://groups.google.com/group/beagleboard?hl=en.\r
+\r
+\r
+\r
+--001636b2ac6d98250e047ca900e4--\r
+++ /dev/null
---- u-boot/cpu/omap3/config.mk-orig 2008-05-27 16:46:45.000000000 -0700
-+++ u-boot/cpu/omap3/config.mk 2008-05-29 12:50:49.000000000 -0700
-@@ -23,7 +23,7 @@
- PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -msoft-float
-
--PLATFORM_CPPFLAGS += -march=armv7a
-+PLATFORM_CPPFLAGS += -march=armv7-a
- # =========================================================================
- #
- # Supply options according to compiler version
+++ /dev/null
-From: Mans Rullgard <mans@mansr.com>
-Date: Mon, 29 Sep 2008 19:56:45 +0000 (+0100)
-Subject: OMAP3: Set MPU clock to 600 MHz
-X-Git-Url: http://git.mansr.com/?p=u-boot;a=commitdiff_plain;h=caccdb772c3028a3e3e801fb1554788150752ffc
-
-OMAP3: Set MPU clock to 600 MHz
----
-
-diff --git a/cpu/omap3/lowlevel_init.S b/cpu/omap3/lowlevel_init.S
-index 1f9a0e9..f95a65f 100644
---- a/cpu/omap3/lowlevel_init.S
-+++ b/cpu/omap3/lowlevel_init.S
-@@ -208,7 +208,7 @@ mpu_dpll_param:
- /* ES1 */
- .word 0x17D,0x0C,0x03,0x01
- /* ES2 */
--.word 0x1F4,0x0C,0x03,0x01
-+.word 0x258,0x0C,0x03,0x01
- /* 3410 */
- .word 0x10A,0x0C,0x03,0x01
-
--- /dev/null
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+Subject: [beagleboard] TI:OMAP: [PATCH 4/4] Minimal Display driver for OMAP3\r
+From: Khasim Syed Mohammed <khasim@beagleboard.org>\r
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+Content-Type: multipart/mixed; boundary=0016e64cc3d48ed9db047ca903b2\r
+\r
+--0016e64cc3d48ed9db047ca903b2\r
+Content-Type: text/plain; charset=ISO-8859-1\r
+\r
+From 239c47a4180fb4d5b5217f892955524d476916cf Mon Sep 17 00:00:00 2001\r
+From: Syed Mohammed Khasim <khasim@ti.com>\r
+Date: Fri, 8 Jan 2010 21:01:44 +0530\r
+Subject: [PATCH] Minimal Display driver for OMAP3\r
+\r
+Supports dynamic configuration of Panel and Video Encoder\r
+Supports Background color on DVID\r
+Supports Color bar on S-Video\r
+\r
+Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>\r
+---\r
+ board/ti/beagle/beagle.c | 13 +++\r
+ board/ti/beagle/beagle.h | 73 ++++++++++++++\r
+ drivers/video/Makefile | 1 +\r
+ drivers/video/omap3_dss.c | 128 +++++++++++++++++++++++++\r
+ include/asm-arm/arch-omap3/dss.h | 193 ++++++++++++++++++++++++++++++++++++++\r
+ include/configs/omap3_beagle.h | 1 +\r
+ 6 files changed, 409 insertions(+), 0 deletions(-)\r
+ create mode 100644 drivers/video/omap3_dss.c\r
+ create mode 100644 include/asm-arm/arch-omap3/dss.h\r
+\r
+diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c\r
+index 7985ee9..29e47c8 100644\r
+--- a/board/ti/beagle/beagle.c\r
++++ b/board/ti/beagle/beagle.c\r
+@@ -114,6 +114,17 @@ void beagle_identify(void)\r
+ }\r
+\r
+ /*\r
++ * Configure DSS to display background color on DVID\r
++ * Configure VENC to display color bar on S-Video\r
++ */\r
++void display_init(void)\r
++{\r
++ omap3_dss_venc_config(&venc_config_std_tv);\r
++ omap3_dss_panel_config(&dvid_cfg);\r
++ omap3_dss_set_background_col(DVI_BEAGLE_ORANGE_COL);\r
++}\r
++\r
++/*\r
+ * Routine: misc_init_r\r
+ * Description: Configure board specific parts\r
+ */\r
+@@ -122,6 +133,7 @@ int misc_init_r(void)\r
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;\r
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;\r
+\r
++ display_init();\r
+ beagle_identify();\r
+\r
+ twl4030_power_init();\r
+@@ -154,6 +166,7 @@ int misc_init_r(void)\r
+ writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |\r
+ GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);\r
+\r
++ omap3_dss_enable();\r
+ dieid_num_r();\r
+\r
+ return 0;\r
+diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h\r
+index b1720c9..7f6769f 100644\r
+--- a/board/ti/beagle/beagle.h\r
++++ b/board/ti/beagle/beagle.h\r
+@@ -23,6 +23,8 @@\r
+ #ifndef _BEAGLE_H_\r
+ #define _BEAGLE_H_\r
+\r
++#include <asm/arch/dss.h>\r
++\r
+ const omap3_sysinfo sysinfo = {\r
+ DDR_STACKED,\r
+ "OMAP3 Beagle board",\r
+@@ -385,4 +387,75 @@ const omap3_sysinfo sysinfo = {\r
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\\r
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\r
+\r
++/*\r
++ * Display Configuration\r
++ */\r
++\r
++#define DVI_BEAGLE_ORANGE_COL 0x00FF8000\r
++\r
++/*\r
++ * Configure VENC in DSS for Beagle to generate Color Bar\r
++ *\r
++ * Kindly refer to OMAP TRM for definition of these values.\r
++ */\r
++static const struct venc_config venc_config_std_tv = {\r
++ .status = 0x0000001B,\r
++ .f_control = 0x00000040,\r
++ .vidout_ctrl = 0x00000000,\r
++ .sync_ctrl = 0x00008000,\r
++ .llen = 0x00008359,\r
++ .flens = 0x0000020C,\r
++ .hfltr_ctrl = 0x00000000,\r
++ .cc_carr_wss_carr = 0x043F2631,\r
++ .c_phase = 0x00000024,\r
++ .gain_u = 0x00000130,\r
++ .gain_v = 0x00000198,\r
++ .gain_y = 0x000001C0,\r
++ .black_level = 0x0000006A,\r
++ .blank_level = 0x0000005C,\r
++ .x_color = 0x00000000,\r
++ .m_control = 0x00000001,\r
++ .bstamp_wss_data = 0x0000003F,\r
++ .s_carr = 0x21F07C1F,\r
++ .line21 = 0x00000000,\r
++ .ln_sel = 0x00000015,\r
++ .l21__wc_ctl = 0x00001400,\r
++ .htrigger_vtrigger = 0x00000000,\r
++ .savid__eavid = 0x069300F4,\r
++ .flen__fal = 0x0016020C,\r
++ .lal__phase_reset = 0x00060107,\r
++ .hs_int_start_stop_x = 0x008D034E,\r
++ .hs_ext_start_stop_x = 0x000F0359,\r
++ .vs_int_start_x = 0x01A00000,\r
++ .vs_int_stop_x__vs_int_start_y = 0x020501A0,\r
++ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,\r
++ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,\r
++ .vs_ext_stop_y = 0x00000006,\r
++ .avid_start_stop_x = 0x03480079,\r
++ .avid_start_stop_y = 0x02040024,\r
++ .fid_int_start_x__fid_int_start_y = 0x0001008A,\r
++ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,\r
++ .fid_ext_start_y__fid_ext_offset_y = 0x01060006,\r
++ .tvdetgp_int_start_stop_x = 0x00140001,\r
++ .tvdetgp_int_start_stop_y = 0x00010001,\r
++ .gen_ctrl = 0x00FF0000,\r
++ .output_control = 0x0000000D,\r
++ .dac_b__dac_c = 0x00000000,\r
++ .height_width = 0x00ef027f\r
++};\r
++\r
++/*\r
++ * Configure Timings for DVI D\r
++ */\r
++static const struct panel_config dvid_cfg = {\r
++ .timing_h = 0x0ff03f31, /* Horizantal timing */\r
++ .timing_v = 0x01400504, /* Vertical timing */\r
++ .pol_freq = 0x00007028, /* Pol Freq */\r
++ .divisor = 0x00010006, /* 72Mhz Pixel Clock */\r
++ .lcd_size = 0x02ff03ff, /* 1024x768 */\r
++ .panel_type = 0x01, /* TFT */\r
++ .data_lines = 0x03, /* 24 Bit RGB */\r
++ .load_mode = 0x02 /* Frame Mode */\r
++};\r
++\r
+ #endif\r
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile\r
+index bb6b5a0..cb15dc2 100644\r
+--- a/drivers/video/Makefile\r
++++ b/drivers/video/Makefile\r
+@@ -37,6 +37,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o\r
+ COBJS-$(CONFIG_VIDEO_SM501) += sm501.o\r
+ COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o\r
+ COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o\r
++COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o\r
+ COBJS-y += videomodes.o\r
+\r
+ COBJS := $(COBJS-y)\r
+diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c\r
+new file mode 100644\r
+index 0000000..2ead7b9\r
+--- /dev/null\r
++++ b/drivers/video/omap3_dss.c\r
+@@ -0,0 +1,128 @@\r
++/*\r
++ * (C) Copyright 2010\r
++ * Texas Instruments, <www.ti.com>\r
++ * Syed Mohammed Khasim <khasim@ti.com>\r
++ *\r
++ * Referred to Linux DSS driver files for OMAP3\r
++ *\r
++ * See file CREDITS for list of people who contributed to this\r
++ * project.\r
++ *\r
++ * This program is free software; you can redistribute it and/or\r
++ * modify it under the terms of the GNU General Public License as\r
++ * published by the Free Software Foundation's version 2 of\r
++ * the License.\r
++ *\r
++ * This program is distributed in the hope that it will be useful,\r
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
++ * GNU General Public License for more details.\r
++ *\r
++ * You should have received a copy of the GNU General Public License\r
++ * along with this program; if not, write to the Free Software\r
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
++ * MA 02111-1307 USA\r
++ */\r
++\r
++#include <common.h>\r
++#include <asm/io.h>\r
++#include <asm/arch/dss.h>\r
++\r
++/*\r
++ * VENC configuration\r
++ */\r
++void omap3_dss_venc_config(const struct venc_config *venc_cfg)\r
++{\r
++ dss_write_reg(VENC_STATUS, venc_cfg->status);\r
++ dss_write_reg(VENC_F_CONTROL, venc_cfg->f_control);\r
++ dss_write_reg(VENC_VIDOUT_CTRL, venc_cfg->vidout_ctrl);\r
++ dss_write_reg(VENC_SYNC_CTRL, venc_cfg->sync_ctrl);\r
++ dss_write_reg(VENC_LLEN, venc_cfg->llen);\r
++ dss_write_reg(VENC_FLENS, venc_cfg->flens);\r
++ dss_write_reg(VENC_HFLTR_CTRL, venc_cfg->hfltr_ctrl);\r
++ dss_write_reg(VENC_CC_CARR_WSS_CARR, venc_cfg->cc_carr_wss_carr);\r
++ dss_write_reg(VENC_C_PHASE, venc_cfg->c_phase);\r
++ dss_write_reg(VENC_GAIN_U, venc_cfg->gain_u);\r
++ dss_write_reg(VENC_GAIN_V, venc_cfg->gain_v);\r
++ dss_write_reg(VENC_GAIN_Y, venc_cfg->gain_y);\r
++ dss_write_reg(VENC_BLACK_LEVEL, venc_cfg->black_level);\r
++ dss_write_reg(VENC_BLANK_LEVEL, venc_cfg->blank_level);\r
++ dss_write_reg(VENC_X_COLOR, venc_cfg->x_color);\r
++ dss_write_reg(VENC_M_CONTROL, venc_cfg->m_control);\r
++ dss_write_reg(VENC_BSTAMP_WSS_DATA, venc_cfg->bstamp_wss_data);\r
++ dss_write_reg(VENC_S_CARR, venc_cfg->s_carr);\r
++ dss_write_reg(VENC_LINE21, venc_cfg->line21);\r
++ dss_write_reg(VENC_LN_SEL, venc_cfg->ln_sel);\r
++ dss_write_reg(VENC_L21__WC_CTL, venc_cfg->l21__wc_ctl);\r
++ dss_write_reg(VENC_HTRIGGER_VTRIGGER, venc_cfg->htrigger_vtrigger);\r
++ dss_write_reg(VENC_SAVID__EAVID, venc_cfg->savid__eavid);\r
++ dss_write_reg(VENC_FLEN__FAL, venc_cfg->flen__fal);\r
++ dss_write_reg(VENC_LAL__PHASE_RESET, venc_cfg->lal__phase_reset);\r
++ dss_write_reg(VENC_HS_INT_START_STOP_X,\r
++ venc_cfg->hs_int_start_stop_x);\r
++ dss_write_reg(VENC_HS_EXT_START_STOP_X,\r
++ venc_cfg->hs_ext_start_stop_x);\r
++ dss_write_reg(VENC_VS_INT_START_X, venc_cfg->vs_int_start_x);\r
++ dss_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,\r
++ venc_cfg->vs_int_stop_x__vs_int_start_y);\r
++ dss_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,\r
++ venc_cfg->vs_int_stop_y__vs_ext_start_x);\r
++ dss_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,\r
++ venc_cfg->vs_ext_stop_x__vs_ext_start_y);\r
++ dss_write_reg(VENC_VS_EXT_STOP_Y, venc_cfg->vs_ext_stop_y);\r
++ dss_write_reg(VENC_AVID_START_STOP_X, venc_cfg->avid_start_stop_x);\r
++ dss_write_reg(VENC_AVID_START_STOP_Y, venc_cfg->avid_start_stop_y);\r
++ dss_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,\r
++ venc_cfg->fid_int_start_x__fid_int_start_y);\r
++ dss_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,\r
++ venc_cfg->fid_int_offset_y__fid_ext_start_x);\r
++ dss_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,\r
++ venc_cfg->fid_ext_start_y__fid_ext_offset_y);\r
++ dss_write_reg(VENC_TVDETGP_INT_START_STOP_X,\r
++ venc_cfg->tvdetgp_int_start_stop_x);\r
++ dss_write_reg(VENC_TVDETGP_INT_START_STOP_Y,\r
++ venc_cfg->tvdetgp_int_start_stop_y);\r
++ dss_write_reg(VENC_GEN_CTRL, venc_cfg->gen_ctrl);\r
++ dss_write_reg(VENC_OUTPUT_CONTROL, venc_cfg->output_control);\r
++ dss_write_reg(VENC_DAC_B__DAC_C, venc_cfg->dac_b__dac_c);\r
++ dss_write_reg(DISPC_SIZE_DIG, venc_cfg->height_width);\r
++ dss_write_reg(DSS_CONTROL, VENC_DSS_CONFIG);\r
++}\r
++\r
++/*\r
++ * Configure Panel Specific parameters\r
++ */\r
++void omap3_dss_panel_config(const struct panel_config *panel_cfg)\r
++{\r
++ dss_write_reg(DISPC_TIMING_H, panel_cfg->timing_h);\r
++ dss_write_reg(DISPC_TIMING_V, panel_cfg->timing_v);\r
++ dss_write_reg(DISPC_POL_FREQ, panel_cfg->pol_freq);\r
++ dss_write_reg(DISPC_DIVISOR, panel_cfg->divisor);\r
++ dss_write_reg(DISPC_SIZE_LCD, panel_cfg->lcd_size);\r
++ dss_write_reg(DISPC_CONFIG,\r
++ (panel_cfg->load_mode << FRAME_MODE_OFFSET));\r
++ dss_write_reg(DISPC_CONTROL,\r
++ ((panel_cfg->panel_type << TFTSTN_OFFSET) |\r
++ (panel_cfg->data_lines << DATALINES_OFFSET)));\r
++}\r
++\r
++/*\r
++ * Enable LCD and DIGITAL OUT in DSS\r
++ */\r
++void omap3_dss_enable(void)\r
++{\r
++ u32 l = 0;\r
++\r
++ l = dss_read_reg(DISPC_CONTROL);\r
++ l |= DISPC_ENABLE;\r
++\r
++ dss_write_reg(DISPC_CONTROL, l);\r
++}\r
++\r
++/*\r
++ * Set Background Color in DISPC\r
++ */\r
++void omap3_dss_set_background_col(u32 color)\r
++{\r
++ dss_write_reg(DISPC_DEFAULT_COLOR0, color);\r
++}\r
+diff --git a/include/asm-arm/arch-omap3/dss.h b/include/asm-arm/arch-omap3/dss.h\r
+new file mode 100644\r
+index 0000000..08c7d8d\r
+--- /dev/null\r
++++ b/include/asm-arm/arch-omap3/dss.h\r
+@@ -0,0 +1,193 @@\r
++/*\r
++ * (C) Copyright 2010\r
++ * Texas Instruments, <www.ti.com>\r
++ * Syed Mohammed Khasim <khasim@ti.com>\r
++ *\r
++ * Referred to Linux DSS driver files for OMAP3\r
++ *\r
++ * See file CREDITS for list of people who contributed to this\r
++ * project.\r
++ *\r
++ * This program is free software; you can redistribute it and/or\r
++ * modify it under the terms of the GNU General Public License as\r
++ * published by the Free Software Foundation's version 2 of\r
++ * the License.\r
++ *\r
++ * This program is distributed in the hope that it will be useful,\r
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
++ * GNU General Public License for more details.\r
++ *\r
++ * You should have received a copy of the GNU General Public License\r
++ * along with this program; if not, write to the Free Software\r
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
++ * MA 02111-1307 USA\r
++ */\r
++\r
++#ifndef DSS_H\r
++#define DSS_H\r
++\r
++/* VENC Register address */\r
++#define VENC_REV_ID 0x48050C00\r
++#define VENC_STATUS 0x48050C04\r
++#define VENC_F_CONTROL 0x48050C08\r
++#define VENC_VIDOUT_CTRL 0x48050C10\r
++#define VENC_SYNC_CTRL 0x48050C14\r
++#define VENC_LLEN 0x48050C1C\r
++#define VENC_FLENS 0x48050C20\r
++#define VENC_HFLTR_CTRL 0x48050C24\r
++#define VENC_CC_CARR_WSS_CARR 0x48050C28\r
++#define VENC_C_PHASE 0x48050C2C\r
++#define VENC_GAIN_U 0x48050C30\r
++#define VENC_GAIN_V 0x48050C34\r
++#define VENC_GAIN_Y 0x48050C38\r
++#define VENC_BLACK_LEVEL 0x48050C3C\r
++#define VENC_BLANK_LEVEL 0x48050C40\r
++#define VENC_X_COLOR 0x48050C44\r
++#define VENC_M_CONTROL 0x48050C48\r
++#define VENC_BSTAMP_WSS_DATA 0x48050C4C\r
++#define VENC_S_CARR 0x48050C50\r
++#define VENC_LINE21 0x48050C54\r
++#define VENC_LN_SEL 0x48050C58\r
++#define VENC_L21__WC_CTL 0x48050C5C\r
++#define VENC_HTRIGGER_VTRIGGER 0x48050C60\r
++#define VENC_SAVID__EAVID 0x48050C64\r
++#define VENC_FLEN__FAL 0x48050C68\r
++#define VENC_LAL__PHASE_RESET 0x48050C6C\r
++#define VENC_HS_INT_START_STOP_X 0x48050C70\r
++#define VENC_HS_EXT_START_STOP_X 0x48050C74\r
++#define VENC_VS_INT_START_X 0x48050C78\r
++#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x48050C7C\r
++#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x48050C80\r
++#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x48050C84\r
++#define VENC_VS_EXT_STOP_Y 0x48050C88\r
++#define VENC_AVID_START_STOP_X 0x48050C90\r
++#define VENC_AVID_START_STOP_Y 0x48050C94\r
++#define VENC_FID_INT_START_X__FID_INT_START_Y 0x48050CA0\r
++#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0x48050CA4\r
++#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0x48050CA8\r
++#define VENC_TVDETGP_INT_START_STOP_X 0x48050CB0\r
++#define VENC_TVDETGP_INT_START_STOP_Y 0x48050CB4\r
++#define VENC_GEN_CTRL 0x48050CB8\r
++#define VENC_OUTPUT_CONTROL 0x48050CC4\r
++#define VENC_DAC_B__DAC_C 0x48050CC8\r
++\r
++/* DSS register addresses */\r
++#define DSS_SYSCONFIG 0x48050010\r
++#define DSS_CONTROL 0x48050040\r
++\r
++/* DISPC register addresses */\r
++#define DISPC_SYSCONFIG 0x48050410\r
++#define DISPC_SYSSTATUS 0x48050414\r
++#define DISPC_CONTROL 0x48050440\r
++#define DISPC_CONFIG 0x48050444\r
++#define DISPC_DEFAULT_COLOR0 0x4805044c\r
++#define DISPC_DEFAULT_COLOR1 0x48050450\r
++#define DISPC_TRANS_COLOR0 0x48050454\r
++#define DISPC_TRANS_COLOR1 0x48050458\r
++#define DISPC_TIMING_H 0x48050464\r
++#define DISPC_TIMING_V 0x48050468\r
++#define DISPC_POL_FREQ 0x4805046c\r
++#define DISPC_DIVISOR 0x48050470\r
++#define DISPC_SIZE_DIG 0x48050478\r
++#define DISPC_SIZE_LCD 0x4805047c\r
++\r
++/* Few Register Offsets */\r
++#define FRAME_MODE_OFFSET 1\r
++#define TFTSTN_OFFSET 3\r
++#define DATALINES_OFFSET 8\r
++\r
++/* Enabling Display controller */\r
++#define LCD_ENABLE 1\r
++#define DIG_ENABLE (1 << 1)\r
++#define GO_LCD (1 << 5)\r
++#define GO_DIG (1 << 6)\r
++#define GP_OUT0 (1 << 15)\r
++#define GP_OUT1 (1 << 16)\r
++\r
++#define DISPC_ENABLE (LCD_ENABLE | \\r
++ DIG_ENABLE | \\r
++ GO_LCD | \\r
++ GO_DIG | \\r
++ GP_OUT0| \\r
++ GP_OUT1)\r
++/* Configure VENC DSS Params */\r
++#define VENC_CLK_ENABLE (1 << 3)\r
++#define DAC_DEMEN (1 << 4)\r
++#define DAC_POWERDN (1 << 5)\r
++#define VENC_OUT_SEL (1 << 6)\r
++\r
++#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \\r
++ DAC_DEMEN | \\r
++ DAC_POWERDN | \\r
++ VENC_OUT_SEL)\r
++\r
++struct venc_config {\r
++ u32 status;\r
++ u32 f_control;\r
++ u32 vidout_ctrl;\r
++ u32 sync_ctrl;\r
++ u32 llen;\r
++ u32 flens;\r
++ u32 hfltr_ctrl;\r
++ u32 cc_carr_wss_carr;\r
++ u32 c_phase;\r
++ u32 gain_u;\r
++ u32 gain_v;\r
++ u32 gain_y;\r
++ u32 black_level;\r
++ u32 blank_level;\r
++ u32 x_color;\r
++ u32 m_control;\r
++ u32 bstamp_wss_data;\r
++ u32 s_carr;\r
++ u32 line21;\r
++ u32 ln_sel;\r
++ u32 l21__wc_ctl;\r
++ u32 htrigger_vtrigger;\r
++ u32 savid__eavid;\r
++ u32 flen__fal;\r
++ u32 lal__phase_reset;\r
++ u32 hs_int_start_stop_x;\r
++ u32 hs_ext_start_stop_x;\r
++ u32 vs_int_start_x;\r
++ u32 vs_int_stop_x__vs_int_start_y;\r
++ u32 vs_int_stop_y__vs_ext_start_x;\r
++ u32 vs_ext_stop_x__vs_ext_start_y;\r
++ u32 vs_ext_stop_y;\r
++ u32 avid_start_stop_x;\r
++ u32 avid_start_stop_y;\r
++ u32 fid_int_start_x__fid_int_start_y;\r
++ u32 fid_int_offset_y__fid_ext_start_x;\r
++ u32 fid_ext_start_y__fid_ext_offset_y;\r
++ u32 tvdetgp_int_start_stop_x;\r
++ u32 tvdetgp_int_start_stop_y;\r
++ u32 gen_ctrl;\r
++ u32 output_control;\r
++ u32 dac_b__dac_c;\r
++ u32 height_width;\r
++};\r
++\r
++struct panel_config {\r
++ u32 timing_h;\r
++ u32 timing_v;\r
++ u32 pol_freq;\r
++ u32 divisor;\r
++ u32 lcd_size;\r
++ u32 panel_type;\r
++ u32 data_lines;\r
++ u32 load_mode;\r
++};\r
++\r
++static inline void dss_write_reg(int reg, u32 val)\r
++{\r
++ __raw_writel(val, reg);\r
++}\r
++\r
++static inline u32 dss_read_reg(int reg)\r
++{\r
++ u32 l = __raw_readl(reg);\r
++ return l;\r
++}\r
++\r
++#endif /* DSS_H */\r
+diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h\r
+index ff6d432..2c15df9 100644\r
+--- a/include/configs/omap3_beagle.h\r
++++ b/include/configs/omap3_beagle.h\r
+@@ -120,6 +120,7 @@\r
+ #define CONFIG_CMD_I2C /* I2C serial bus support */\r
+ #define CONFIG_CMD_MMC /* MMC support */\r
+ #define CONFIG_CMD_NAND /* NAND support */\r
++#define CONFIG_VIDEO_OMAP3 /* DSS Support */\r
+\r
+ #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */\r
+ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */\r
+-- \r
+1.5.6.3\r
+\r
+--0016e64cc3d48ed9db047ca903b2\r
+Content-Type: text/plain; charset=ISO-8859-1\r
+\r
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+Date: Fri, 8 Jan 2010 21:08:59 +0530\r
+Message-ID: <a8ca84ad1001080738q6f5aeca1gd276ed5846b0db43@mail.gmail.com>\r
+Subject: [beagleboard] TI:OMAP: [PATCH 2/4] Enable I2C bus switching\r
+From: Khasim Syed Mohammed <khasim@beagleboard.org>\r
+To: u-boot@lists.denx.de, beagleboard@googlegroups.com\r
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+Content-Type: multipart/mixed; boundary=0016e64cc3d48ce7bb047ca8fca8\r
+\r
+--0016e64cc3d48ce7bb047ca8fca8\r
+Content-Type: text/plain; charset=ISO-8859-1\r
+\r
+From 9045377f255e8a59450a6957e63366b4963281ae Mon Sep 17 00:00:00 2001\r
+From: Syed Mohammed Khasim <khasim@ti.com>\r
+Date: Fri, 8 Jan 2010 20:20:41 +0530\r
+Subject: [PATCH] Enable I2C bus switching\r
+\r
+OMAP3 supports Multiple I2C channels, this patch allows\r
+us to use i2c dev <bus no> command to switch between busses.\r
+\r
+Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>\r
+Acked-by: Heiko Schocher <hs@denx.de>\r
+---\r
+ drivers/i2c/omap24xx_i2c.c | 5 +++++\r
+ include/configs/omap3_beagle.h | 4 ++++\r
+ 2 files changed, 9 insertions(+), 0 deletions(-)\r
+\r
+diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c\r
+index ff18991..e8c8184 100644\r
+--- a/drivers/i2c/omap24xx_i2c.c\r
++++ b/drivers/i2c/omap24xx_i2c.c\r
+@@ -435,3 +435,8 @@ int i2c_set_bus_num(unsigned int bus)\r
+\r
+ return 0;\r
+ }\r
++\r
++int i2c_get_bus_num(void)\r
++{\r
++ return (int) current_bus;\r
++}\r
+diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h\r
+index d1c9cd0..ff6d432 100644\r
+--- a/include/configs/omap3_beagle.h\r
++++ b/include/configs/omap3_beagle.h\r
+@@ -100,6 +100,10 @@\r
+ /* DDR - I use Micron DDR */\r
+ #define CONFIG_OMAP3_MICRON_DDR 1\r
+\r
++/* Enable Multi Bus support for I2C */\r
++#define CONFIG_I2C_MULTI_BUS 1\r
++#define CONFIG_SYS_I2C_NOPROBES {0x0, 0x0}\r
++\r
+ /* commands to include */\r
+ #include <config_cmd_default.h>\r
+\r
+-- \r
+1.5.6.3\r
+\r
+--0016e64cc3d48ce7bb047ca8fca8\r
+Content-Type: text/plain; charset=ISO-8859-1\r
+\r
+-- \r
+You received this message because you are subscribed to the Google Groups "Beagle Board" group.\r
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+\r
+\r
+\r
+--0016e64cc3d48ce7bb047ca8fca8--\r
+++ /dev/null
-From: Mans Rullgard <mans@mansr.com>
-Date: Thu, 2 Oct 2008 01:25:35 +0000 (+0100)
-Subject: OMAP3: Beagleboard can have dual-chip RAM
-X-Git-Url: http://git.mansr.com/?p=u-boot;a=commitdiff_plain;h=ef6ee5af8d584bddadb2d45ad4320cef96b8a934;hp=caccdb772c3028a3e3e801fb1554788150752ffc
-
-OMAP3: Beagleboard can have dual-chip RAM
-
-Some Beagleboards are fitted with dual-chip RAM. Returning DDR_STACKED
-from get_mem_type() causes the second chip (on CS1) to be enabled.
-
-FIXME: need a better way to configure this.
-
-Signed-off-by: Mans Rullgard <mans@mansr.com>
----
-
-diff --git a/cpu/omap3/board.c b/cpu/omap3/board.c
-index 804021f..f7cf289 100644
---- a/cpu/omap3/board.c
-+++ b/cpu/omap3/board.c
-@@ -265,15 +265,17 @@ int dram_init(void)
- * where it can be started. Early init code will init
- * memory on CS0.
- */
-- if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED))
-+ if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
- do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
-+ make_cs1_contiguous();
-+ }
-
- size0 = get_sdr_cs_size(SDRC_CS0_OSET);
- size1 = get_sdr_cs_size(SDRC_CS1_OSET);
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
-- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
-+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(1);
- gd->bd->bi_dram[1].size = size1;
-
- return 0;
-diff --git a/cpu/omap3/mem.c b/cpu/omap3/mem.c
-index 955fa70..53687a5 100644
---- a/cpu/omap3/mem.c
-+++ b/cpu/omap3/mem.c
-@@ -114,12 +114,12 @@ void make_cs1_contiguous(void)
- * for a part. Helps in guessing which part
- * we are currently using.
- *******************************************************/
--u32 mem_ok(void)
-+u32 mem_ok(u32 cs)
- {
- u32 val1, val2, addr;
- u32 pattern = 0x12345678;
-
-- addr = OMAP34XX_SDRC_CS0;
-+ addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
-
- __raw_writel(0x0, addr + 0x400); /* clear pos A */
- __raw_writel(pattern, addr); /* pattern to pos B */
-@@ -156,43 +156,40 @@ void sdrc_init(void)
-
- void do_sdrc_init(u32 offset, u32 early)
- {
-+ u32 actim_offs = offset? 0x28: 0;
-
-- /* reset sdrc controller */
-- __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
-- wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
-- __raw_writel(0, SDRC_SYSCONFIG);
-+ if (early) {
-+ /* reset sdrc controller */
-+ __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
-+ wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
-+ __raw_writel(0, SDRC_SYSCONFIG);
-
-- /* setup sdrc to ball mux */
-- __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
-+ /* setup sdrc to ball mux */
-+ __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
-
-- /* SDRC_MCFG0 register */
-- (*(unsigned int *) 0x6D000080) = 0x02584099; /* from Micron */
-+ /* Disble Power Down of CKE cuz of 1 CKE on combo part */
-+ __raw_writel(0x00000081, SDRC_POWER);
-
-- /* SDRC_RFR_CTRL0 register */
-- (*(unsigned int *) 0x6D0000a4) = 0x54601; /* for 166M */
-+ __raw_writel(0x0000A, SDRC_DLLA_CTRL);
-+ sdelay(0x20000);
-+ }
-
-- /* SDRC_ACTIM_CTRLA0 register */
-- (*(unsigned int *) 0x6D00009c) = 0xa29db4c6; /* for 166M */
-+ __raw_writel(0x02584099, SDRC_MCFG_0 + offset);
-+ __raw_writel(0x4e201, SDRC_RFR_CTRL + offset);
-+ __raw_writel(0xaa9db4c6, SDRC_ACTIM_CTRLA_0 + actim_offs);
-+ __raw_writel(0x11517, SDRC_ACTIM_CTRLB_0 + actim_offs);
-
-- /* SDRC_ACTIM_CTRLB0 register */
-- (*(unsigned int *) 0x6D0000a0) = 0x12214; /* for 166M */
-+ __raw_writel(CMD_NOP, SDRC_MANUAL_0 + offset);
-+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0 + offset);
-+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset);
-+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset);
-
-- /* Disble Power Down of CKE cuz of 1 CKE on combo part */
-- (*(unsigned int *) 0x6D000070) = 0x00000081;
-+ /* CAS latency 3, Write Burst = Read Burst, Serial Mode,
-+ Burst length = 4 */
-+ __raw_writel(0x00000032, SDRC_MR_0 + offset);
-
-- /* SDRC_Manual command register */
-- (*(unsigned int *) 0x6D0000a8) = 0x00000000; /* NOP command */
-- (*(unsigned int *) 0x6D0000a8) = 0x00000001; /* Precharge command */
-- (*(unsigned int *) 0x6D0000a8) = 0x00000002; /* Auto-refresh command */
-- (*(unsigned int *) 0x6D0000a8) = 0x00000002; /* Auto-refresh command */
--
-- /* SDRC MR0 register */
-- (*(int *) 0x6D000084) = 0x00000032; /* Burst length = 4 */
-- /* CAS latency = 3, Write Burst = Read Burst Serial Mode */
--
-- /* SDRC DLLA control register */
-- (*(unsigned int *) 0x6D000060) = 0x0000A;
-- sdelay(0x20000);
-+ if (!mem_ok(offset))
-+ __raw_writel(0, SDRC_MCFG_0 + offset);
- }
-
- void enable_gpmc_config(u32 *gpmc_config, u32 gpmc_base, u32 base, u32 size)
-diff --git a/cpu/omap3/sys_info.c b/cpu/omap3/sys_info.c
-index 12cf5ba..64d9e7e 100644
---- a/cpu/omap3/sys_info.c
-+++ b/cpu/omap3/sys_info.c
-@@ -90,8 +90,11 @@ u32 is_mem_sdr(void)
- ***********************************************************/
- u32 get_mem_type(void)
- {
-- /* Current SDP3430 uses 2x16 MDDR Infenion parts */
-+#ifdef CONFIG_OMAP3_BEAGLE
-+ return DDR_STACKED;
-+#else
- return DDR_DISCRETE;
-+#endif
- }
-
- /***********************************************************************
-@@ -109,6 +112,22 @@ u32 get_sdr_cs_size(u32 offset)
- }
-
- /***********************************************************************
-+ * get_sdr_cs_offset() - get offset of cs from cs0 start
-+ ************************************************************************/
-+u32 get_sdr_cs_offset(u32 cs)
-+{
-+ u32 offset;
-+
-+ if (!cs)
-+ return 0;
-+
-+ offset = __raw_readl(SDRC_CS_CFG);
-+ offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
-+
-+ return offset;
-+}
-+
-+/***********************************************************************
- * get_board_type() - get board type based on current production stats.
- * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
- * when they are available we can get info from there. This should
-diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
-index d47defb..df2d150 100644
---- a/include/asm-arm/arch-omap3/cpu.h
-+++ b/include/asm-arm/arch-omap3/cpu.h
-@@ -123,7 +123,6 @@
- #define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE+0xC4)
- #define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE+0xC8)
- #define SDRC_RFR_CTRL (OMAP34XX_SDRC_BASE+0xA4)
--#define SDRC_RFR_CTRL (OMAP34XX_SDRC_BASE+0xA4)
- #define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE+0xA8)
- #define OMAP34XX_SDRC_CS0 0x80000000
- #define OMAP34XX_SDRC_CS1 0xA0000000
-diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
-index 279bdce..5b0bd9e 100644
---- a/include/asm-arm/arch-omap3/sys_proto.h
-+++ b/include/asm-arm/arch-omap3/sys_proto.h
-@@ -50,6 +50,7 @@ u32 get_gpmc0_width(void);
- u32 get_board_type(void);
- void display_board_info(u32);
- u32 get_sdr_cs_size(u32 offset);
-+u32 get_sdr_cs_offset(u32 cs);
- u32 running_in_sdram(void);
- u32 running_in_sram(void);
- u32 running_in_flash(void);
+++ /dev/null
---- git/Makefile.orig 2008-07-25 16:21:22.000000000 -0700
-+++ git/Makefile 2008-07-27 06:49:08.000000000 -0700
-@@ -2582,8 +2582,8 @@ SMN42_config : unconfig
- #########################################################################
- ## ARM CORTEX Systems
- #########################################################################
--omap3530beagle_config : unconfig
-- @$(MKCONFIG) $(@:_config=) arm omap3 omap3530beagle
-+beagleboard_config : unconfig
-+ @$(MKCONFIG) omap3530beagle arm omap3 omap3530beagle
-
- overo_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm omap3 overo
-
--- /dev/null
+Delivered-To: koen@beagleboard.org\r
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+Date: Fri, 8 Jan 2010 21:07:50 +0530\r
+Message-ID: <a8ca84ad1001080737r2312270ao80aa04ce60cc780@mail.gmail.com>\r
+Subject: [beagleboard] TI:OMAP: [PATCH 1/4] OMAP3 Beagle Update revision \r
+ detection\r
+From: Khasim Syed Mohammed <khasim@beagleboard.org>\r
+To: u-boot@lists.denx.de, beagleboard@googlegroups.com\r
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+\r
+--0016e64cc3d4779e0f047ca8f8bb\r
+Content-Type: text/plain; charset=ISO-8859-1\r
+\r
+From 15fbe5ff9ee2fd2f8da4c16805d6c7ccf7244bae Mon Sep 17 00:00:00 2001\r
+From: Syed Mohammed Khasim <khasim@ti.com>\r
+Date: Fri, 8 Jan 2010 20:13:47 +0530\r
+Subject: [PATCH] OMAP3 Beagle Update revision detection\r
+\r
+New BeagleBoard revision C4 uses a new ID. Update revision detection.\r
+\r
+Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>\r
+Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>\r
+---\r
+ board/ti/beagle/beagle.c | 65 ++++++++++++++++++++++++++++-----------------\r
+ board/ti/beagle/beagle.h | 8 ++++-\r
+ 2 files changed, 46 insertions(+), 27 deletions(-)\r
+\r
+diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c\r
+index 32d501e..0def5a6 100644\r
+--- a/board/ti/beagle/beagle.c\r
++++ b/board/ti/beagle/beagle.c\r
+@@ -38,7 +38,7 @@\r
+ #include <asm/mach-types.h>\r
+ #include "beagle.h"\r
+\r
+-static int beagle_revision_c;\r
++static int beagle_revision;\r
+\r
+ /*\r
+ * Routine: board_init\r
+@@ -60,41 +60,57 @@ int board_init(void)\r
+ /*\r
+ * Routine: beagle_get_revision\r
+ * Description: Return the revision of the BeagleBoard this code is running on.\r
+- * If it is a revision Ax/Bx board, this function returns 0,\r
+- * on a revision C board you will get a 1.\r
+ */\r
+ int beagle_get_revision(void)\r
+ {\r
+- return beagle_revision_c;\r
++ return beagle_revision;\r
+ }\r
+\r
+ /*\r
+ * Routine: beagle_identify\r
+- * Description: Detect if we are running on a Beagle revision Ax/Bx or\r
+- * Cx. This can be done by GPIO_171. If this is low, we are\r
+- * running on a revision C board.\r
++ * Description: Detect if we are running on a Beagle revision Ax/Bx,\r
++ * C1/2/3, C4 or D. This can be done by reading\r
++ * the level of GPIO173, GPIO172 and GPIO171. This should\r
++ * result in\r
++ * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx\r
++ * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3\r
++ * GPIO173, GPIO172, GPIO171: 1 0 1 => C4\r
++ * GPIO173, GPIO172, GPIO171: 0 0 0 => D\r
+ */\r
+ void beagle_identify(void)\r
+ {\r
+- beagle_revision_c = 0;\r
+- if (!omap_request_gpio(171)) {\r
+- unsigned int val;\r
+-\r
+- omap_set_gpio_direction(171, 1);\r
+- val = omap_get_gpio_datain(171);\r
+- omap_free_gpio(171);\r
+-\r
+- if (val)\r
+- beagle_revision_c = 0;\r
+- else\r
+- beagle_revision_c = 1;\r
+- }\r
++ omap_request_gpio(171);\r
++ omap_request_gpio(172);\r
++ omap_request_gpio(173);\r
++ omap_set_gpio_direction(171, 1);\r
++ omap_set_gpio_direction(172, 1);\r
++ omap_set_gpio_direction(173, 1);\r
++\r
++ beagle_revision = omap_get_gpio_datain(173) << 2 |\r
++ omap_get_gpio_datain(172) << 1 |\r
++ omap_get_gpio_datain(171);\r
++ omap_free_gpio(171);\r
++ omap_free_gpio(172);\r
++ omap_free_gpio(173);\r
+\r
+ printf("Board revision ");\r
+- if (beagle_revision_c)\r
+- printf("C\n");\r
+- else\r
++\r
++ switch (beagle_revision) {\r
++ case REVISION_AXBX:\r
+ printf("Ax/Bx\n");\r
++ break;\r
++ case REVISION_CX:\r
++ printf("C1/C2/C3\n");\r
++ break;\r
++ case REVISION_C4:\r
++ printf("C4\n");\r
++ break;\r
++ case REVISION_D:\r
++ printf("D\n");\r
++ break;\r
++ default:\r
++ printf("unknown 0x%02x\n", beagle_revision);\r
++ }\r
+ }\r
+\r
+ /*\r
+@@ -137,7 +153,6 @@ void set_muxconf_regs(void)\r
+ {\r
+ MUX_BEAGLE();\r
+\r
+- if (beagle_revision_c) {\r
++ if (beagle_revision != REVISION_AXBX)\r
+ MUX_BEAGLE_C();\r
+- }\r
+ }\r
+diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h\r
+index 7fe6275..b1720c9 100644\r
+--- a/board/ti/beagle/beagle.h\r
++++ b/board/ti/beagle/beagle.h\r
+@@ -33,7 +33,11 @@ const omap3_sysinfo sysinfo = {\r
+ #endif\r
+ };\r
+\r
+-#define BOARD_REVISION_MASK (0x1 << 11)\r
++/* BeagleBoard revisions */\r
++#define REVISION_AXBX 0x7\r
++#define REVISION_CX 0x6\r
++#define REVISION_C4 0x5\r
++#define REVISION_D 0x0\r
+\r
+ /*\r
+ * IEN - Input Enable\r
+@@ -264,7 +268,7 @@ const omap3_sysinfo sysinfo = {\r
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\\r
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\\r
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\\r
+- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\\r
++ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\\r
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\\r
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\\r
+ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\\r
+-- \r
+1.5.6.3\r
+\r
+--0016e64cc3d4779e0f047ca8f8bb\r
+Content-Type: text/plain; charset=ISO-8859-1\r
+\r
+-- \r
+You received this message because you are subscribed to the Google Groups "Beagle Board" group.\r
+To post to this group, send email to beagleboard@googlegroups.com.\r
+To unsubscribe from this group, send email to beagleboard+unsubscribe@googlegroups.com.\r
+For more options, visit this group at http://groups.google.com/group/beagleboard?hl=en.\r
+\r
+\r
+\r
+--0016e64cc3d4779e0f047ca8f8bb--\r
SRC_URI_beagleboard = "git://git.denx.de/u-boot-ti.git;protocol=git \
file://fw_env.config \
file://new-pinmux.patch;patch=1 \
+file://revision-detection.patch;patch=1 \
+file://i2c.patch;patch=1 \
+file://720MHz.patch;patch=1 \
+file://dss.patch;patch=1 \
"
-SRCREV_beagleboard = "1590f84007e2b50ad346a482fff89195cb04ff4e"
-PV_beagleboard = "2009.08+${PR}+gitr${SRCREV}"
+
+SRCREV_beagleboard = "a5cf522a91ba479d459f8221135bdb3e9ae97479"
+PV_beagleboard = "2009.11-rc1+${PR}+gitr${SRCREV}"
SRCREV_calamari = "f67066b6b0740b826ed862615c5ab022aaf4779a"
PV_calamari = "2009.08+${PR}+gitr${SRCREV}"
git.openpandora.org / openembedded.git / commitdiff