Convert CONFIG_FSL_MEMAC et al to Kconfig
authorTom Rini <trini@konsulko.com>
Sat, 23 Jul 2022 17:05:10 +0000 (13:05 -0400)
committerTom Rini <trini@konsulko.com>
Thu, 4 Aug 2022 20:18:48 +0000 (16:18 -0400)
This converts the following to Kconfig:
   CONFIG_FSL_MEMAC
   CONFIG_SYS_MEMAC_LITTLE_ENDIAN

Signed-off-by: Tom Rini <trini@konsulko.com>
44 files changed:
arch/arm/include/asm/arch-fsl-layerscape/config.h
configs/ls1088aqds_defconfig
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
configs/ls1088aqds_qspi_defconfig
configs/ls1088aqds_sdcard_ifc_defconfig
configs/ls1088aqds_sdcard_qspi_defconfig
configs/ls1088aqds_tfa_defconfig
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_qspi_defconfig
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_sdcard_qspi_defconfig
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
configs/ls1088ardb_tfa_defconfig
configs/ls2080aqds_SECURE_BOOT_defconfig
configs/ls2080aqds_defconfig
configs/ls2080aqds_nand_defconfig
configs/ls2080aqds_qspi_defconfig
configs/ls2080aqds_sdcard_defconfig
configs/ls2080ardb_SECURE_BOOT_defconfig
configs/ls2080ardb_defconfig
configs/ls2080ardb_nand_defconfig
configs/ls2081ardb_defconfig
configs/ls2088aqds_tfa_defconfig
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
configs/ls2088ardb_qspi_defconfig
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
configs/ls2088ardb_tfa_defconfig
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
configs/lx2160aqds_tfa_defconfig
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
configs/lx2160ardb_tfa_defconfig
configs/lx2160ardb_tfa_stmm_defconfig
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
configs/lx2162aqds_tfa_defconfig
configs/lx2162aqds_tfa_verified_boot_defconfig
configs/ten64_tfa_defconfig
drivers/net/Kconfig
drivers/net/fm/Makefile
drivers/net/phy/Kconfig
include/configs/ls1088aqds.h
include/configs/ls1088ardb.h
include/configs/ls2080aqds.h
include/configs/ls2080ardb.h
include/configs/lx2160a_common.h

index f6710d0..76e07f3 100644 (file)
@@ -40,8 +40,6 @@
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE                      0x06000000
 #define GICR_BASE                      0x06100000
@@ -49,8 +47,6 @@
 /* SMMU Defintions */
 #define SMMU_BASE                      0x05000000 /* GR0 Base */
 
-/* DCFG - GUR */
-
 /* Cache Coherent Interconnect */
 #define CCI_MN_BASE                    0x04000000
 #define CCI_MN_RNF_NODEID_LIST         0x180
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* DCFG - GUR */
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000 /* initial RAM */
 #define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE                              0x06000000
 #define GICR_BASE                              0x06200000
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* SEC */
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 
index bd34f8d..aca271a 100644 (file)
@@ -89,6 +89,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 3af10a0..9bed029 100644 (file)
@@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 55a5389..4a56e43 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 3aa20d3..d203fb9 100644 (file)
@@ -108,6 +108,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index fa1f71d..1bd83af 100644 (file)
@@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 91899d2..c59de47 100644 (file)
@@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index b4cae48..aa9bc8a 100644 (file)
@@ -78,6 +78,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 452ee83..2459212 100644 (file)
@@ -81,6 +81,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index e36512e..fc222b5 100644 (file)
@@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 2f81a13..eba206d 100644 (file)
@@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index b5f556d..347cc60 100644 (file)
@@ -77,6 +77,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 3af7828..362b4be 100644 (file)
@@ -83,6 +83,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 965863d..a414387 100644 (file)
@@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 3e0da68..91b5226 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 1d841af..7d3cce0 100644 (file)
@@ -97,6 +97,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 302de32..6bb3781 100644 (file)
@@ -77,6 +77,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index e972842..e2710b8 100644 (file)
@@ -91,6 +91,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 16367fc..1d0aea0 100644 (file)
@@ -80,6 +80,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x580980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index 82ad9b2..ec6869c 100644 (file)
@@ -83,6 +83,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x580980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index 189a4e0..fa929ac 100644 (file)
@@ -102,6 +102,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index fb7faa4..e6e6fe6 100644 (file)
@@ -72,6 +72,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index 2eba6b6..2a7cbd3 100644 (file)
@@ -95,6 +95,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index b86f816..5d9c48b 100644 (file)
@@ -71,6 +71,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 9e08552..0628cc2 100644 (file)
@@ -78,6 +78,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 0c58a6d..5fb1346 100644 (file)
@@ -86,6 +86,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index a7c7036..bf9a016 100644 (file)
@@ -94,6 +94,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index b2bc71a..21c6052 100644 (file)
@@ -82,6 +82,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index 32e47c3..62b214b 100644 (file)
@@ -89,6 +89,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index a758a4d..65e43bf 100644 (file)
@@ -75,6 +75,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index e6e7940..8cdebc8 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index bbdcb89..c7e9afe 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index bb81e56..ca70f8b 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index 216ac80..68cdefb 100644 (file)
@@ -92,6 +92,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index b7a4238..ee3134e 100644 (file)
@@ -93,6 +93,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index 4bbee30..dad6c2d 100644 (file)
@@ -71,6 +71,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 21d6481..93e7dbe 100644 (file)
@@ -375,6 +375,7 @@ config SYS_QE_FMAN_FW_LENGTH
 
 config SYS_FMAN_V3
        bool
+       select FSL_MEMAC
        help
          SoC has FMan v3 with mEMAC
 
index ae38412..5a7d303 100644 (file)
@@ -11,7 +11,6 @@ obj-y += tgec.o
 obj-y += tgec_phy.o
 
 # Soc have FMAN v3 with mEMAC
-obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
 obj-$(CONFIG_SYS_FMAN_V3) += memac.o
 
 # SoC specific SERDES support
index 33a4b6f..52ce08b 100644 (file)
@@ -345,6 +345,13 @@ config PHY_NCSI
 
 endif #PHYLIB
 
+config FSL_MEMAC
+       bool "NXP mEMAC PHY support"
+
+config SYS_MEMAC_LITTLE_ENDIAN
+       bool "mEMAC is access in little endian mode"
+       depends on FSL_MEMAC || FSL_LS_MDIO
+
 config PHY_RESET_DELAY
        int "Extra delay after reset before MII register access"
        default 0
index 6db0ba5..747ee9d 100644 (file)
 #endif
 #endif
 
-#define CONFIG_FSL_MEMAC
-
 #define COMMON_ENV \
        "kernelheader_addr_r=0x80200000\0"      \
        "fdtheader_addr_r=0x80100000\0"         \
 #endif
 
 #ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_FSL_MEMAC
 #define RGMII_PHY1_ADDR                0x1
 #define RGMII_PHY2_ADDR                0x2
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
index c3e87ed..3e829ea 100644 (file)
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM              0
 
-#define CONFIG_FSL_MEMAC
-
 #ifndef SPL_NO_ENV
 /* Initial environment variables */
 #ifdef CONFIG_TFABOOT
index f6efda2..6487397 100644 (file)
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
 
-#define CONFIG_FSL_MEMAC
-
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #ifdef CONFIG_NXP_ESBC
 #endif
 
 #if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_FSL_MEMAC
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
index c6b601d..87d07b7 100644 (file)
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
 
-#define CONFIG_FSL_MEMAC
-
 #define BOOT_TARGET_DEVICES(func) \
        func(USB, usb, 0) \
        func(MMC, mmc, 0) \
index b754373..0f5b044 100644 (file)
@@ -10,8 +10,6 @@
 #include <asm/arch/config.h>
 #include <asm/arch/soc.h>
 
-#define CONFIG_FSL_MEMAC
-
 #define CONFIG_SYS_FLASH_BASE          0x20000000
 
 /* DDR */