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drm/radeon: implement async vm_flush for the sDMA (v6)
authorAlex Deucher <alexander.deucher@amd.com>
Mon, 22 Oct 2012 17:04:03 +0000 (13:04 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Jun 2013 21:50:33 +0000 (17:50 -0400)
Update the page table base address and flush the
VM TLB using the sDMA.

V2: update for 2 level PTs
V3: update vm flush
V4: update SH_MEM* regs
V5: switch back to old style VM TLB invalidate
V6: fix packet formatting

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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