ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores

Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

diff --git a/Documentation/devicetree/bindings/arc/axs103.txt b/Documentation/devicetree/bindings/arc/axs103.txt
new file mode 100644 (file)
index 0000000..6eea862
--- /dev/null
+++ b/Documentation/devicetree/bindings/arc/axs103.txt
@@ -0,0 +1,8 @@
+Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
+---------------------------------------------------------------------------
+
+SDP Main Board with an AXC003 FPGA Card which can contain various flavours of
+HS38x cores.
+
+Required root node properties:
+    - compatible = "snps,axs103", "snps,arc-sdp";

diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
new file mode 100644 (file)
index 0000000..15c8d62
--- /dev/null
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Device tree for AXC003 CPU card: HS38x UP configuration
+ */
+
+/ {
+       compatible = "snps,arc";
+       clock-frequency = <75000000>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpu_card {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               ranges = <0x00000000 0xf0000000 0x10000000>;
+
+               cpu_intc: archs-intc@cpu {
+                       compatible = "snps,archs-intc";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+               };
+
+               /*
+                * this GPIO block ORs all interrupts on CPU card (creg,..)
+                * to uplink only 1 IRQ to ARC core intc
+                */
+               dw-apb-gpio@0x2000 {
+                       compatible = "snps,dw-apb-gpio";
+                       reg = < 0x2000 0x80 >;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       ictl_intc: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <30>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupt-parent = <&cpu_intc>;
+                               interrupts = <25>;
+                       };
+               };
+
+               debug_uart: dw-apb-uart@0x5000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x5000 0x100>;
+                       clock-frequency = <33333000>;
+                       interrupt-parent = <&ictl_intc>;
+                       interrupts = <2 4>;
+                       baud = <115200>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+               };
+
+               arcpct0: pct {
+                       compatible = "snps,archs-pct";
+                       #interrupt-cells = <1>;
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <20>;
+               };
+       };
+
+       /*
+        * This INTC is actually connected to DW APB GPIO
+        * which acts as a wire between MB INTC and CPU INTC.
+        * GPIO INTC is configured in platform init code
+        * and here we mimic direct connection from MB INTC to
+        * CPU INTC, thus we set "interrupts = <7>" instead of
+        * "interrupts = <12>"
+        *
+        * This intc actually resides on MB, but we move it here to
+        * avoid duplicating the MB dtsi file given that IRQ from
+        * this intc to cpu intc are different for axs101 and axs103
+        */
+       mb_intc: dw-apb-ictl@0xe0012000 {
+               #interrupt-cells = <1>;
+               compatible = "snps,dw-apb-ictl";
+               reg = < 0xe0012000 0x200 >;
+               interrupt-controller;
+               interrupt-parent = <&cpu_intc>;
+               interrupts = < 24 >;
+       };
+
+       memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x00000000 0x80000000 0x40000000>;
+               device_type = "memory";
+               reg = <0x00000000 0x20000000>;  /* 512MiB */
+       };
+};

diff --cc arch/arc/boot/dts/axc003_idu.dtsi
Simple merge

diff --cc arch/arc/boot/dts/axs103.dts
Simple merge

diff --cc arch/arc/boot/dts/axs103_idu.dts
Simple merge

diff --cc arch/arc/configs/axs103_defconfig
Simple merge

diff --cc arch/arc/configs/axs103_smp_defconfig
Simple merge

diff --cc arch/arc/kernel/devtree.c
Simple merge

diff --cc arch/arc/plat-axs10x/Kconfig
Simple merge

diff --cc arch/arc/plat-axs10x/axs10x.c
Simple merge