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drm/nouveau/clock: fix missing pll type/addr when matching default entry
authorBen Skeggs <bskeggs@redhat.com>
Mon, 22 Oct 2012 04:10:16 +0000 (14:10 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Mon, 22 Oct 2012 04:38:06 +0000 (14:38 +1000)
This issue is a regression from 70790f4f819875e8f390871fd15bbbf823f28e1b,
and causes us to miss a special-case for C51 (NV4E) chipsets and return
the wrong reference frequency for the VPLLs.

Should fix fdo#56202

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

No differences found
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