arm64: zynqmp: Aligned QSPI configuration with latest spec
authorMichal Simek <michal.simek@amd.com>
Fri, 22 Sep 2023 10:35:43 +0000 (12:35 +0200)
committerMichal Simek <michal.simek@amd.com>
Mon, 9 Oct 2023 08:25:32 +0000 (10:25 +0200)
Official DT binding description for dual stacked/paralllel configurations
have been merged that's why switch to it.

Link: https://lore.kernel.org/r/20220126112608.955728-3-miquel.raynal@bootlin.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2912091c231f5e945ee44601c285fe16263448da.1695378830.git.michal.simek@amd.com
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
arch/arm/dts/zynqmp-zcu102-revA.dts
arch/arm/dts/zynqmp-zcu106-revA.dts
arch/arm/dts/zynqmp-zcu111-revA.dts
arch/arm/dts/zynqmp-zcu208-revA.dts
arch/arm/dts/zynqmp-zcu216-revA.dts

index 4fcb466..e72ed50 100644 (file)
 
 &qspi {
        status = "okay";
+       num-cs = <2>;
        flash@0 {
                compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
                #address-cells = <1>;
                #size-cells = <1>;
-               reg = <0x0>;
+               reg = <0>, <1>;
+               parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
                spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
index 025e651..be75ca6 100644 (file)
 &qspi {
        status = "okay";
        is-dual = <1>;
+       num-cs = <2>;
        flash@0 {
                compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
                #address-cells = <1>;
                #size-cells = <1>;
-               reg = <0x0>;
+               reg = <0>, <1>;
+               parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
                spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
index 776373d..6cae681 100644 (file)
 &qspi {
        status = "okay";
        is-dual = <1>;
+       num-cs = <2>;
        flash@0 {
                compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
                #address-cells = <1>;
                #size-cells = <1>;
-               reg = <0x0>;
+               reg = <0>, <1>;
+               parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
                spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
index 62a8be9..d088652 100644 (file)
 &qspi {
        status = "okay";
        is-dual = <1>;
+       num-cs = <2>;
        flash@0 {
                compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
                #address-cells = <1>;
                #size-cells = <1>;
-               reg = <0x0>;
+               reg = <0>, <1>;
+               parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
                spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
index 0c1f509..7028881 100644 (file)
 &qspi {
        status = "okay";
        is-dual = <1>;
+       num-cs = <2>;
        flash@0 {
                compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
                #address-cells = <1>;
                #size-cells = <1>;
-               reg = <0>;
+               reg = <0>, <1>;
+               parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
                spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
index 8ca01f0..989ac28 100644 (file)
 &qspi {
        status = "okay";
        is-dual = <1>;
+       num-cs = <2>;
        flash@0 {
                compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
                #address-cells = <1>;
                #size-cells = <1>;
-               reg = <0x0>;
+               reg = <0>, <1>;
+               parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
                spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */