arm: dts: rockchip: Add rk3528-u-boot.dtsi

Add a rk3528-u-boot.dtsi extending the basic dts/upstream rk3528.dtsi
with bare minimum nodes to have a booting system from eMMC and SD-card.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi
new file mode 100644 (file)
index 0000000..eb6a55c
--- /dev/null
+++ b/arch/arm/dts/rk3528-u-boot.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+       aliases {
+               mmc0 = &sdhci;
+               mmc1 = &sdmmc;
+       };
+
+       chosen {
+               u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+       };
+
+       dmc {
+               compatible = "rockchip,rk3528-dmc";
+               bootph-all;
+       };
+
+       soc {
+               rng: rng@ffc50000 {
+                       compatible = "rockchip,rkrng";
+                       reg = <0x0 0xffc50000 0x0 0x200>;
+               };
+
+               otp: nvmem@ffce0000 {
+                       compatible = "rockchip,rk3528-otp";
+                       reg = <0x0 0xffce0000 0x0 0x4000>;
+               };
+
+               sdmmc: mmc@ffc30000 {
+                       compatible = "rockchip,rk3528-dw-mshc",
+                                    "rockchip,rk3288-dw-mshc";
+                       reg = <0x0 0xffc30000 0x0 0x4000>;
+                       clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
+                       clock-names = "biu", "ciu";
+                       fifo-depth = <0x100>;
+                       interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+                       max-frequency = <150000000>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
+                                   <&sdmmc_det>;
+                       resets = <&cru SRST_H_SDMMC0>;
+                       reset-names = "reset";
+                       rockchip,default-sample-phase = <90>;
+                       status = "disabled";
+               };
+       };
+};
+
+&cru {
+       bootph-all;
+};
+
+&emmc_bus8 {
+       bootph-pre-ram;
+       bootph-some-ram;
+};
+
+&emmc_clk {
+       bootph-pre-ram;
+       bootph-some-ram;
+};
+
+&emmc_cmd {
+       bootph-pre-ram;
+       bootph-some-ram;
+};
+
+&emmc_strb {
+       bootph-pre-ram;
+       bootph-some-ram;
+};
+
+&gmac0_clk {
+       bootph-all;
+};
+
+&ioc_grf {
+       bootph-all;
+};
+
+&otp {
+       bootph-some-ram;
+};
+
+&pcfg_pull_none {
+       bootph-all;
+};
+
+&pcfg_pull_up {
+       bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+       bootph-pre-ram;
+       bootph-some-ram;
+};
+
+&pinctrl {
+       bootph-all;
+};
+
+&sdhci {
+       bootph-pre-ram;
+       bootph-some-ram;
+       u-boot,spl-fifo-mode;
+};
+
+&sdmmc {
+       bootph-pre-ram;
+       bootph-some-ram;
+       u-boot,spl-fifo-mode;
+};
+
+&sdmmc_bus4 {
+       bootph-pre-ram;
+       bootph-some-ram;
+};
+
+&sdmmc_clk {
+       bootph-pre-ram;
+       bootph-some-ram;
+};
+
+&sdmmc_cmd {
+       bootph-pre-ram;
+       bootph-some-ram;
+};
+
+&sdmmc_det {
+       bootph-pre-ram;
+       bootph-some-ram;
+};
+
+&uart0 {
+       bootph-all;
+       clock-frequency = <24000000>;
+};
+
+&uart0m0_xfer {
+       bootph-pre-sram;
+       bootph-pre-ram;
+};
+
+&xin24m {
+       bootph-all;
+};