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drm/radeon/si: properly set up the clearstate buffer for pg (v2)
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 13 Aug 2013 16:48:06 +0000 (12:48 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 30 Aug 2013 20:30:53 +0000 (16:30 -0400)
The format of the clearstate buffer used for pg (powergating)
changed between NI and SI.  This formats it properly for what
the hardware expects on SI.

v2: fix addresses

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

No differences found
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