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drm/i915: Fix VLV eDP timing v2
authorChon Ming Lee <chon.ming.lee@intel.com>
Wed, 25 Sep 2013 07:47:51 +0000 (15:47 +0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 1 Oct 2013 05:45:22 +0000 (07:45 +0200)
Fix the typo in previous commit for DP 1.62 divisor.
drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2

v2: sigh, the m1 div is 3.

Reported-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

No differences found
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