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ARM: meson: DTS: enable L2 cache
authorBeniamino Galvani <b.galvani@gmail.com>
Tue, 18 Nov 2014 14:30:35 +0000 (15:30 +0100)
committerCarlo Caione <carlo@caione.org>
Tue, 18 Nov 2014 15:36:14 +0000 (16:36 +0100)
This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>

No differences found
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