arm64: dts: rockchip: Add clock generators for RK3528 SoC

Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 858cdcdd11cf9913756297d3869e4de0f01329ea ]

(cherry picked from commit 60741472b42e92d2393327cb70669ab90e3b382f)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index e58faa9..37fd403 100644 (file)
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/rockchip,rk3528-cru.h>
 
 / {
        compatible = "rockchip,rk3528";
@@ -95,6 +96,13 @@
                #clock-cells = <0>;
        };
 
+       gmac0_clk: clock-gmac50m {
+               compatible = "fixed-clock";
+               clock-frequency = <50000000>;
+               clock-output-names = "gmac0";
+               #clock-cells = <0>;
+       };
+
        soc {
                compatible = "simple-bus";
                ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
@@ -114,6 +122,49 @@
                        #interrupt-cells = <3>;
                };
 
+               cru: clock-controller@ff4a0000 {
+                       compatible = "rockchip,rk3528-cru";
+                       reg = <0x0 0xff4a0000 0x0 0x30000>;
+                       assigned-clocks =
+                               <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>,
+                               <&cru PLL_PPLL>, <&cru PLL_CPLL>,
+                               <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>,
+                               <&cru CLK_MATRIX_500M_SRC>,
+                               <&cru CLK_MATRIX_50M_SRC>,
+                               <&cru CLK_MATRIX_100M_SRC>,
+                               <&cru CLK_MATRIX_150M_SRC>,
+                               <&cru CLK_MATRIX_200M_SRC>,
+                               <&cru CLK_MATRIX_300M_SRC>,
+                               <&cru CLK_MATRIX_339M_SRC>,
+                               <&cru CLK_MATRIX_400M_SRC>,
+                               <&cru CLK_MATRIX_600M_SRC>,
+                               <&cru CLK_PPLL_50M_MATRIX>,
+                               <&cru CLK_PPLL_100M_MATRIX>,
+                               <&cru CLK_PPLL_125M_MATRIX>,
+                               <&cru ACLK_BUS_VOPGL_ROOT>;
+                       assigned-clock-rates =
+                               <32768>, <1188000000>,
+                               <1000000000>, <996000000>,
+                               <408000000>, <250000000>,
+                               <500000000>,
+                               <50000000>,
+                               <100000000>,
+                               <150000000>,
+                               <200000000>,
+                               <300000000>,
+                               <340000000>,
+                               <400000000>,
+                               <600000000>,
+                               <50000000>,
+                               <100000000>,
+                               <125000000>,
+                               <500000000>;
+                       clocks = <&xin24m>, <&gmac0_clk>;
+                       clock-names = "xin24m", "gmac0";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
                uart0: serial@ff9f0000 {
                        compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
                        reg = <0x0 0xff9f0000 0x0 0x100>;