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clk: tegra: initialise parent of uart clocks
authorLaxman Dewangan <ldewangan@nvidia.com>
Tue, 12 Feb 2013 15:17:59 +0000 (20:47 +0530)
committerStephen Warren <swarren@nvidia.com>
Wed, 13 Feb 2013 18:17:03 +0000 (11:17 -0700)
Initialise the parent of UARTs to PLLP and disabling clock by
default.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

No differences found
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