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arm64: Execute DSB during thread switching for TLB/cache maintenance
authorCatalin Marinas <catalin.marinas@arm.com>
Wed, 24 Apr 2013 13:47:02 +0000 (14:47 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Thu, 25 Apr 2013 16:45:48 +0000 (17:45 +0100)
The DSB following TLB or cache maintenance ops must be run on the same
CPU. With kernel preemption enabled or for user-space cache maintenance
this may not be the case. This patch adds an explicit DSB in the
__switch_to() function.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

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