riscv: dts: jh7110: Make u-boot device trees adapting to upstream DT

Add u-boot features to the U-Boot device tree.

Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
index 3012466..45fada3 100644 (file)
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -6,6 +6,10 @@
 #include "binman.dtsi"
 #include "jh7110-u-boot.dtsi"
 / {
+       aliases {
+               spi0 = &qspi;
+       };
+
        chosen {
                bootph-pre-ram;
        };
@@ -27,6 +31,9 @@
 
 &uart0 {
        bootph-pre-ram;
+       reg-offset = <0>;
+       current-speed = <115200>;
+       clock-frequency = <24000000>;
 };
 
 &mmc0 {
@@ -40,29 +47,43 @@
 &qspi {
        bootph-pre-ram;
 
-       nor-flash@0 {
+       flash@0 {
                bootph-pre-ram;
+               cdns,read-delay = <2>;
+               spi-max-frequency = <100000000>;
        };
 };
 
+&syscrg {
+       assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+                         <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+                         <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+                         <&syscrg JH7110_SYSCLK_QSPI_REF>;
+       assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+                                <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+                                <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+                                <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+       assigned-clock-rates = <0>, <0>, <0>, <0>;
+};
+
 &sysgpio {
        bootph-pre-ram;
 };
 
 &mmc0_pins {
        bootph-pre-ram;
-       mmc0-pins-rest {
+       rst-pins {
                bootph-pre-ram;
        };
 };
 
 &mmc1_pins {
        bootph-pre-ram;
-       mmc1-pins0 {
+       clk-pins {
                bootph-pre-ram;
        };
 
-       mmc1-pins1 {
+       mmc-pins {
                bootph-pre-ram;
        };
 };
@@ -78,6 +99,9 @@
        bootph-pre-ram;
        eeprom@50 {
                bootph-pre-ram;
+               compatible = "atmel,24c04";
+               reg = <0x50>;
+               pagesize = <16>;
        };
 };
 

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index 52c1d60..ce7d9e1 100644 (file)
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -46,6 +46,15 @@
                };
        };
 
+       timer {
+               compatible = "riscv,timer";
+               interrupts-extended = <&cpu0_intc 5>,
+                                     <&cpu1_intc 5>,
+                                     <&cpu2_intc 5>,
+                                     <&cpu3_intc 5>,
+                                     <&cpu4_intc 5>;
+       };
+
        soc {
                bootph-pre-ram;
 
@@ -73,10 +82,22 @@
        bootph-pre-ram;
 };
 
+&gmac0_rgmii_rxin {
+       bootph-pre-ram;
+};
+
 &gmac0_rmii_refin {
        bootph-pre-ram;
 };
 
+&gmac1_rgmii_rxin {
+       bootph-pre-ram;
+};
+
+&gmac1_rmii_refin {
+       bootph-pre-ram;
+};
+
 &aoncrg {
        bootph-pre-ram;
 };
@@ -92,7 +113,3 @@
 &sys_syscon {
        bootph-pre-ram;
 };
-
-&S7_0 {
-       status = "okay";
-};