DEPENDS = "mpfr gmp"
-INC_PR = "r1"
+INC_PR = "r2"
SRC_URI = "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \
file://fedora/gcc43-c++-builtin-redecl.patch;patch=1;pnum=0 \
file://gcc-flags-for-build.patch;patch=1 \
file://gcc-pr36218.patch;patch=1 \
file://gcc-4.3.3-SYSROOT_CFLAGS_FOR_TARGET.patch;patch=1 \
- file://arm-gcc-objective.patch;patch=1 \
+ file://arm-gcc-objective.patch;patch=1 \
+ file://arm-rev.patch;patch=1 \
+ file://arm-rev-fix.patch;patch=1 \
"
SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch;patch=1 "
--- /dev/null
+commit aa1f316a6cd8a058cfb95f5b0431b0b544c58734
+Author: ramana <ramana@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Wed Sep 8 21:35:48 2010 +0000
+
+ 2010-09-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ PR target/44392
+ * config/arm/arm.md (bswapsi2): Handle condition correctly
+ for armv6 and optimize_size.
+
+ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@164029 138bc75d-0d04-0410-961f-82ee72b054a4
+
+ Conflicts:
+ gcc/ChangeLog
+
+diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
+index 7dcad98..d83acc8 100644
+--- a/gcc/config/arm/arm.md
++++ b/gcc/config/arm/arm.md
+@@ -10963,34 +10963,29 @@
+ (define_expand "bswapsi2"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
+-"TARGET_EITHER"
++"TARGET_EITHER && (arm_arch6 || !optimize_size)"
+ "
+- if (!arm_arch6)
+- {
+- if (!optimize_size)
+- {
+- rtx op2 = gen_reg_rtx (SImode);
+- rtx op3 = gen_reg_rtx (SImode);
++ if (!arm_arch6)
++ {
++ rtx op2 = gen_reg_rtx (SImode);
++ rtx op3 = gen_reg_rtx (SImode);
+
+- if (TARGET_THUMB)
+- {
+- rtx op4 = gen_reg_rtx (SImode);
+- rtx op5 = gen_reg_rtx (SImode);
++ if (TARGET_THUMB)
++ {
++ rtx op4 = gen_reg_rtx (SImode);
++ rtx op5 = gen_reg_rtx (SImode);
+
+- emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
+- op2, op3, op4, op5));
+- }
+- else
+- {
+- emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
+- op2, op3));
+- }
++ emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
++ op2, op3, op4, op5));
++ }
++ else
++ {
++ emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
++ op2, op3));
++ }
+
+- DONE;
+- }
+- else
+- FAIL;
+- }
++ DONE;
++ }
+ "
+ )
+
--- /dev/null
+commit ff82f7574960d02bc45ef4d6b0cad1f310144ae1
+Author: ramana <ramana@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Thu Jan 28 08:35:59 2010 +0000
+
+ Fix bswap patterns for trunk.
+
+ Committed by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ 2010-01-28 Stephen Thomas <stephen.thomas@arm.com>
+
+ * config/arm/arm.md (bswapsi2): Add support for bswapsi2.
+ (arm_rev): New.
+ (arm_legacy_rev): Likewise.
+ (thumb_legacy_rev): Likewise.
+
+
+diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
+index e6ae543..7dcad98 100644
+--- a/gcc/config/arm/arm.md
++++ b/gcc/config/arm/arm.md
+@@ -10893,6 +10893,107 @@
+ [(set_attr "conds" "clob")]
+ )
+
++(define_insn "arm_rev"
++ [(set (match_operand:SI 0 "s_register_operand" "=r")
++ (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
++ "TARGET_EITHER && arm_arch6"
++ "rev\t%0, %1"
++ [(set (attr "length")
++ (if_then_else (eq_attr "is_thumb" "yes")
++ (const_int 2)
++ (const_int 4)))]
++)
++
++(define_expand "arm_legacy_rev"
++ [(set (match_operand:SI 2 "s_register_operand" "")
++ (xor:SI (rotatert:SI (match_operand:SI 1 "s_register_operand" "")
++ (const_int 16))
++ (match_dup 1)))
++ (set (match_dup 2)
++ (lshiftrt:SI (match_dup 2)
++ (const_int 8)))
++ (set (match_operand:SI 3 "s_register_operand" "")
++ (rotatert:SI (match_dup 1)
++ (const_int 8)))
++ (set (match_dup 2)
++ (and:SI (match_dup 2)
++ (const_int -65281)))
++ (set (match_operand:SI 0 "s_register_operand" "")
++ (xor:SI (match_dup 3)
++ (match_dup 2)))]
++ "TARGET_32BIT"
++ ""
++)
++
++;; Reuse temporaries to keep register pressure down.
++(define_expand "thumb_legacy_rev"
++ [(set (match_operand:SI 2 "s_register_operand" "")
++ (ashift:SI (match_operand:SI 1 "s_register_operand" "")
++ (const_int 24)))
++ (set (match_operand:SI 3 "s_register_operand" "")
++ (lshiftrt:SI (match_dup 1)
++ (const_int 24)))
++ (set (match_dup 3)
++ (ior:SI (match_dup 3)
++ (match_dup 2)))
++ (set (match_operand:SI 4 "s_register_operand" "")
++ (const_int 16))
++ (set (match_operand:SI 5 "s_register_operand" "")
++ (rotatert:SI (match_dup 1)
++ (match_dup 4)))
++ (set (match_dup 2)
++ (ashift:SI (match_dup 5)
++ (const_int 24)))
++ (set (match_dup 5)
++ (lshiftrt:SI (match_dup 5)
++ (const_int 24)))
++ (set (match_dup 5)
++ (ior:SI (match_dup 5)
++ (match_dup 2)))
++ (set (match_dup 5)
++ (rotatert:SI (match_dup 5)
++ (match_dup 4)))
++ (set (match_operand:SI 0 "s_register_operand" "")
++ (ior:SI (match_dup 5)
++ (match_dup 3)))]
++ "TARGET_THUMB"
++ ""
++)
++
++(define_expand "bswapsi2"
++ [(set (match_operand:SI 0 "s_register_operand" "=r")
++ (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
++"TARGET_EITHER"
++"
++ if (!arm_arch6)
++ {
++ if (!optimize_size)
++ {
++ rtx op2 = gen_reg_rtx (SImode);
++ rtx op3 = gen_reg_rtx (SImode);
++
++ if (TARGET_THUMB)
++ {
++ rtx op4 = gen_reg_rtx (SImode);
++ rtx op5 = gen_reg_rtx (SImode);
++
++ emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
++ op2, op3, op4, op5));
++ }
++ else
++ {
++ emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
++ op2, op3));
++ }
++
++ DONE;
++ }
++ else
++ FAIL;
++ }
++ "
++)
++
+ ;; Load the FPA co-processor patterns
+ (include "fpa.md")
+ ;; Load the Maverick co-processor patterns