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clk: zynqmp: enable topsw_lsbus clock
author
Venkatesh Yadav Abbarapu
<venkatesh.abbarapu@amd.com>
Mon, 4 Dec 2023 08:45:15 +0000
(14:15 +0530)
committer
Michal Simek
<michal.simek@amd.com>
Wed, 13 Dec 2023 15:48:15 +0000
(16:48 +0100)
Display port is using topsw_lsbus clock, it is failing
while enabling the clock, so enable the topsw_lsbus clock.
Signed-off-by: Sreekanth Sunnam <sreekanth.sunnam@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link:
https://lore.kernel.org/r/20231204084515.9488-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
drivers/clk/clk_zynqmp.c
patch
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diff --git
a/drivers/clk/clk_zynqmp.c
b/drivers/clk/clk_zynqmp.c
index
1cfe0e2
..
c059b9e
100644
(file)
--- a/
drivers/clk/clk_zynqmp.c
+++ b/
drivers/clk/clk_zynqmp.c
@@
-844,6
+844,7
@@
static int zynqmp_clk_enable(struct clk *clk)
break;
case qspi_ref ... can1_ref:
case lpd_lsbus:
+ case topsw_lsbus:
clkact_shift = 24;
mask = 0x1;
break;