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drm/radeon: put UVD PLLs in bypass mode
authorChristian König <christian.koenig@amd.com>
Thu, 18 Apr 2013 13:25:58 +0000 (15:25 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 22 Apr 2013 14:39:16 +0000 (10:39 -0400)
Just power down the PLL when we get a VCLK or DCLK of zero.
Enabling the bypass mode early should also allow us to
switch UVD clocks on the fly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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