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drm/i915: Pipe timing registers need an offset on VLV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 24 Jan 2013 13:29:46 +0000 (15:29 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 24 Jan 2013 22:13:13 +0000 (23:13 +0100)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

No differences found
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