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ARM: OMAP3: Fix CM register bit masks
authorRajendra Nayak <rnayak@ti.com>
Tue, 8 May 2012 05:55:21 +0000 (23:55 -0600)
committerPaul Walmsley <paul@pwsan.com>
Tue, 8 May 2012 05:55:21 +0000 (23:55 -0600)
The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL
register are 3 bits wide.  Fix the MASK definition accordingly.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

No differences found
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