# CONFIG_PXA_EZX_E6 is not set
CONFIG_EZX_BP=y
CONFIG_EZX_PCAP=y
+CONFIG_EZX_EOC=y
CONFIG_EZX_EMU=y
CONFIG_EZX_EMU_USB=y
# CONFIG_EZX_EMU_UART is not set
--- /dev/null
+Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c
+===================================================================
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a1200.c 2007-09-07 22:15:52.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c 2007-09-09 13:29:56.000000000 -0300
+@@ -25,6 +25,7 @@
+ #include <asm/arch/mmc.h>
+
+ #include "generic.h"
++#include "ezx-eoc.h"
+
+ extern void ezx_lcd_power(int, struct fb_var_screeninfo *);
+ extern void ezx_backlight_power(int);
+@@ -227,11 +228,69 @@
+ .resource = pcap_ts_resources,
+ };
+
++
++/* EOC */
++static const unsigned int tab_init_eoc_reg[][2] =
++{
++ {POWER_IC_REG_EOC_INT_MASK, 0x00000FEF},
++ {POWER_IC_REG_EOC_POWER_CONTROL_0, 0x00000C00},
++ {POWER_IC_REG_EOC_POWER_CONTROL_1, 0x0000000C},
++ {POWER_IC_REG_EOC_CONN_CONTROL, 0x00021044},
++};
++
++static void dump_eoc_registers(void)
++{
++ int i, val = 0;
++
++ printk("========DUMP EOC=========\n");
++ for (i = 0; i < POWER_IC_REG_EOC_NUM; i++) {
++ eoc_reg_read(i, &val);
++ printk("eoc_registers[%d] = 0x%08X\n", i, val);
++ }
++ printk("========END DUMP=========\n");
++}
++
++/*
++ * FIXME: The same about the PCAP driver applies here.
++ * This is the initial state only.
++ * Which bits does the change to USB/UART/AUDIO mode?
++ * I think that this is causing the crash on pxa27x-udc
++ * you are setting the 'port connected' bit, and thats why
++ * you are getting interrupts early.
++ * --WM
++ */
++
++static int __init a1200_eoc_init(void)
++{
++ int i;
++
++ for (i = 0; i < sizeof(tab_init_eoc_reg)/sizeof(unsigned int)/2; i++)
++ {
++ eoc_reg_write(tab_init_eoc_reg[i][0], tab_init_eoc_reg[i][1]);
++ }
++ dump_eoc_registers();
++ return 0;
++}
++
++static struct ezx_eoc_platform_data a1200_eoc_platform_data = {
++ .init = a1200_eoc_init,
++};
++
++struct platform_device a1200_eoc_device = {
++ .name = "ezx-eoc",
++ .id = -1,
++ .dev = {
++ .platform_data = &a1200_eoc_platform_data,
++ },
++};
++
+ static struct platform_device *devices[] __initdata = {
+ &a1200_pcap_device,
+ &pcap_ts_device,
++ &a1200_eoc_device,
+ };
+
++
+ static void __init a1200_init(void)
+ {
+ set_pxa_fb_info(&a1200_fb_info);
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a1200.c 2007-06-28 22:48:05.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c 2007-06-28 22:53:19.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a1200.c 2007-09-07 11:51:55.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c 2007-09-07 11:54:52.000000000 -0300
@@ -13,6 +13,8 @@
#include <linux/init.h>
#include <linux/platform_device.h>
static struct pxafb_mode_info mode_a1200 = {
.pixclock = 192308,
.xres = 240,
-@@ -88,6 +180,7 @@
+@@ -118,6 +210,7 @@
static void __init a1200_init(void)
{
set_pxa_fb_info(&a1200_fb_info);
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a1200.c 2007-06-28 22:44:12.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c 2007-06-28 22:45:56.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a1200.c 2007-09-07 11:32:32.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c 2007-09-07 11:51:55.000000000 -0300
@@ -19,6 +19,7 @@
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxafb.h>
#include "generic.h"
-@@ -48,7 +49,40 @@
+@@ -48,7 +49,70 @@
.pxafb_lcd_power = &ezx_lcd_power,
};
+/* PCAP */
+static int __init a1200_pcap_init(void)
+{
++ /*
++ * FIXME: this is the PCAP INITIAL STATE.
++ * most of these writes should NOT be done here
++ * * voltage regulators, voltage enablers should be set by the
++ * driver which uses the connected hardware. Otherwise you
++ * drain power unnecessarily.
++ * * interrupt related registers should be set by the irq functions
++ * only. I think that the INT_SEL register selects on which irq
++ * pin the (ap/bp) the irq goes. This should go on ezx-pcap.c, but
++ * only if it actually makes any difference.
++ * * Only power state automatic changes should be done here.
++ * (*LOWPWR, *STBY, LOWPWR*)
++ * * I removed some writes which i consider extremelly wrong. And
++ * which i think will not break anything (they were overwritten
++ * later anyway).
++ *
++ * --WM
++ */
++ ezx_pcap_write(PCAP_REG_INT_SEL, 0x0); /* wrong */
++ ezx_pcap_write(PCAP_REG_SWCTRL, 0x2ee6); /* partially wrong */
++ ezx_pcap_write(PCAP_REG_VREG1, 0x15778e3); /* wrong */
++ ezx_pcap_write(PCAP_REG_VREG2, 0x810234); /* partially wrong */
++ ezx_pcap_write(PCAP_REG_AUXVREG, 0x1024bec); /* wrong */
++ ezx_pcap_write(PCAP_REG_PWR, 0x94108); /* partially wrong */
++ ezx_pcap_write(PCAP_REG_AUXVREG_MASK, 0x214d48); /* wrong */
++ ezx_pcap_write(PCAP_REG_BUSCTRL, 0x2a0); /* wrong */
++ ezx_pcap_write(PCAP_REG_LOWPWR, 0x1d9610c);
++ ezx_pcap_write(PCAP_REG_PERIPH, 0x0); /* wrong */
++ ezx_pcap_write(PCAP_REG_GP, 0x107); /* probably unnecessary */
++
+ return 0;
+}
+
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a1200.c 2007-06-28 22:54:35.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c 2007-06-28 22:55:00.000000000 -0300
-@@ -173,8 +173,33 @@
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a1200.c 2007-09-07 11:54:52.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a1200.c 2007-09-07 11:55:10.000000000 -0300
+@@ -203,8 +203,33 @@
},
};
+/* PCAP_TS */
+struct resource pcap_ts_resources[] = {
+ [0] = {
-+ .start = EZX_IRQ_ADCDONE2,
-+ .end = EZX_IRQ_ADCDONE2,
++ .start = EZX_IRQ_ADCDONE,
++ .end = EZX_IRQ_ADCDONE,
+ .flags = IORESOURCE_IRQ,
+ },
+ [1] = {
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-01 19:46:15.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-01 19:52:09.000000000 -0300
-@@ -219,8 +219,33 @@
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:02:13.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:03:16.000000000 -0300
+@@ -211,8 +211,33 @@
},
};
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-01 19:58:07.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-01 20:02:00.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:58:17.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:59:03.000000000 -0300
@@ -17,6 +17,7 @@
#include <linux/mmc/host.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-@@ -319,10 +320,33 @@
+@@ -311,10 +312,33 @@
.resource = pcap_ts_resources,
};
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-01 19:52:09.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-01 19:56:13.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:03:16.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:05:18.000000000 -0300
@@ -16,6 +16,7 @@
#include <linux/fb.h>
#include <linux/mmc/host.h>
#ifdef CONFIG_EZX_PCAP
extern int ezx_pcap_mmcsd_power(int);
-@@ -243,6 +246,55 @@
+@@ -235,6 +238,55 @@
.resource = a780_emu_resources,
};
static struct platform_device *devices[] __initdata = {
&a780_pcap_device,
&a780_emu_device,
-@@ -263,6 +315,7 @@
+@@ -255,6 +307,7 @@
set_pxa_fb_info(&a780_fb_info);
pxa_set_mci_info(&a780_mci_platform_data);
Index: linux-2.6.21/drivers/leds/Kconfig
===================================================================
---- linux-2.6.21.orig/drivers/leds/Kconfig 2007-08-01 19:38:44.000000000 -0300
-+++ linux-2.6.21/drivers/leds/Kconfig 2007-08-01 20:03:29.000000000 -0300
+--- linux-2.6.21.orig/drivers/leds/Kconfig 2007-08-31 22:27:41.000000000 -0300
++++ linux-2.6.21/drivers/leds/Kconfig 2007-08-31 23:59:27.000000000 -0300
@@ -104,6 +104,13 @@
These triggers allow kernel events to drive the LEDs and can
be configured via sysfs. If unsure, say Y.
depends on LEDS_TRIGGERS
Index: linux-2.6.21/drivers/leds/Makefile
===================================================================
---- linux-2.6.21.orig/drivers/leds/Makefile 2007-08-01 19:38:44.000000000 -0300
-+++ linux-2.6.21/drivers/leds/Makefile 2007-08-01 20:03:29.000000000 -0300
+--- linux-2.6.21.orig/drivers/leds/Makefile 2007-08-31 22:27:41.000000000 -0300
++++ linux-2.6.21/drivers/leds/Makefile 2007-08-31 23:59:27.000000000 -0300
@@ -16,6 +16,7 @@
obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o
obj-$(CONFIG_LEDS_H1940) += leds-h1940.o
Index: linux-2.6.21/drivers/leds/leds-a780.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/drivers/leds/leds-a780.c 2007-08-01 20:03:29.000000000 -0300
++++ linux-2.6.21/drivers/leds/leds-a780.c 2007-08-31 23:59:27.000000000 -0300
@@ -0,0 +1,122 @@
+/*
+ * EZX Platform LED Driver for the Motorola A780 GSM Phone
+{
+ if ( value > 31 ) value = 31;
+ printk( KERN_DEBUG "a780led_main_set: %d\n", value );
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL0, value & 0x01);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL1, value & 0x02);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL2, value & 0x04);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL3, value & 0x08);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL4, value & 0x10);
++ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL_CTRL0, value & 0x01);
++ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL_CTRL1, value & 0x02);
++ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL_CTRL2, value & 0x04);
++ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL_CTRL3, value & 0x08);
++ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL_CTRL4, value & 0x10);
+}
+
+static void a780led_aux_set(struct led_classdev *led_cdev, enum led_brightness value)
+{
+ if ( value > 31 ) value = 31;
+ printk( KERN_DEBUG "a780led_aux_set: %d\n", value );
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL0, value & 0x01);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL1, value & 0x02);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL2, value & 0x04);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL3, value & 0x08);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL4, value & 0x10);
++ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL2_CTRL0, value & 0x01);
++ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL2_CTRL1, value & 0x02);
++ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL2_CTRL2, value & 0x04);
++ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL2_CTRL3, value & 0x08);
++ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL2_CTRL4, value & 0x10);
+}
+
+static struct led_classdev a780_main_led = {
+MODULE_LICENSE("GPL");
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-01 20:02:00.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-01 20:03:29.000000000 -0300
-@@ -341,12 +341,20 @@
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:59:03.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:59:27.000000000 -0300
+@@ -333,12 +333,20 @@
},
};
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-06-28 22:45:00.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-06-28 22:53:03.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:01:54.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:02:13.000000000 -0300
@@ -14,6 +14,8 @@
#include <linux/init.h>
#include <linux/platform_device.h>
static struct pxafb_mode_info mode_a780 = {
.pixclock = 150000,
.xres = 240,
-@@ -145,6 +237,7 @@
+@@ -137,6 +229,7 @@
PSLR = 0x05800f00;
set_pxa_fb_info(&a780_fb_info);
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-06-28 22:44:12.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-06-28 22:45:00.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 22:33:03.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:01:17.000000000 -0300
@@ -20,6 +20,7 @@
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxafb.h>
#include "generic.h"
-@@ -49,7 +50,85 @@
+@@ -49,7 +50,77 @@
.pxafb_lcd_power = &ezx_lcd_power,
};
+static int __init a780_pcap_init(void)
+{
+ /* initialize PCAP registers */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1CTRL, 1);
-+// ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL3);
-+
+ /* set SW1 sleep to keep SW1 1.3v in sync mode */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE10, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE11, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE10, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE11, 0);
+
+ /* SW1 active in sync mode */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE00, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE01, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE00, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE01, 0);
+
+ /* at SW1 -core voltage to 1.30V */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW10_DVS, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW11_DVS, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW12_DVS, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW13_DVS, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW10_DVS, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW11_DVS, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW12_DVS, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW13_DVS, 0);
+
+ /* when STANDY2 PIN ACTIVE (high) set V3-- sram V8 -- pll off */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_LOWPWR, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_LOWPWR, 0);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V3_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V3_LOWPWR, 0);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V8_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V8_LOWPWR, 0);
+
+ /*
+ * when STANDY2 PIN ACTIVE (high) set V4-- lcd only for e680 V6 ---
+ * camera for e680
+ */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_LOWPWR, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_LOWPWR, 0);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V4_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V4_LOWPWR, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V6_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V6_LOWPWR, 0);
+
+ /* set Vc to low power mode when AP sleep */
-+// SSP_PCAP_bit_set( SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VC_STBY);
-+
-+ /* set VAUX2 to voltage 2.775V and low power mode when AP sleep */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_1, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_0, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_LOWPWR, 1);
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN, 1);
++// SSP_PCAP_bit_set(PCAP_BIT_LOWPWR_CTRL_VC_STBY);
+
-+// PGSR(GPIO34_TXENB) |= GPIO_bit(GPIO34_TXENB);
++ /* set VAUX2 to low power mode when AP sleep */
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_VAUX2_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_VAUX2_LOWPWR, 1);
+
+ return 0;
+}
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-01 19:56:13.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-01 19:58:07.000000000 -0300
-@@ -295,9 +295,34 @@
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:05:18.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:06:53.000000000 -0300
+@@ -287,9 +287,34 @@
},
};
Index: linux-2.6.21/drivers/leds/leds-a780.c
===================================================================
---- linux-2.6.21.orig/drivers/leds/leds-a780.c 2007-05-08 15:09:26.000000000 -0300
-+++ linux-2.6.21/drivers/leds/leds-a780.c 2007-05-08 15:19:26.000000000 -0300
-@@ -18,10 +18,13 @@
- #include <linux/leds.h>
- #include <asm/arch/ezx-pcap.h>
-
-+extern void ezx_pcap_vibrator_level(u_int32_t);
-+
- static void a780led_main_set(struct led_classdev *led_cdev, enum led_brightness value)
- {
- if ( value > 31 ) value = 31;
- printk( KERN_DEBUG "a780led_main_set: %d\n", value );
-+#warning FIXME: use read/write operations
- ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL0, value & 0x01);
- ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL1, value & 0x02);
- ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL2, value & 0x04);
-@@ -33,6 +36,7 @@
- {
- if ( value > 31 ) value = 31;
- printk( KERN_DEBUG "a780led_aux_set: %d\n", value );
-+#warning FIXME: use read/write operations
- ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL0, value & 0x01);
- ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL1, value & 0x02);
- ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL2, value & 0x04);
-@@ -40,6 +44,43 @@
- ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL4, value & 0x10);
+--- linux-2.6.21.orig/drivers/leds/leds-a780.c 2007-09-01 00:15:03.000000000 -0300
++++ linux-2.6.21/drivers/leds/leds-a780.c 2007-09-01 00:23:39.000000000 -0300
+@@ -40,6 +40,17 @@
+ ezx_pcap_bit_set(PCAP_BIT_PERIPH_BL2_CTRL4, value & 0x10);
}
+static void a780vibrator_set(struct led_classdev *led_cdev, enum led_brightness value)
+{
-+ if ( value > 4 ) value = 4;
++ if (value > 4) value = 4;
+ printk( KERN_DEBUG "a780vibrator_set: %d\n", value );
-+
-+ switch(value)
-+ {
-+ case 0:
-+ /* turn off vibrator */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN, 0);
-+ break;
-+
-+ case 1:
-+ ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN, 1);
-+ break;
-+
-+ case 2:
-+ ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN, 1);
-+ break;
-+
-+ case 3:
-+ ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL2);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN, 1);
-+ break;
-+
-+ case 4:
-+ ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL3);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN, 1);
-+ break;
-+
-+ default:
-+ break;
-+ }
++ ezx_pcap_vibrator_level(value-1);
++ if (value == 0)
++ ezx_pcap_bit_set(PCAP_BIT_AUXVREG_V_VIB_EN, 0);
++ else
++ ezx_pcap_bit_set(PCAP_BIT_AUXVREG_V_VIB_EN, 1);
+}
+
static struct led_classdev a780_main_led = {
.name = "a780:main",
.default_trigger = "none",
-@@ -52,11 +93,18 @@
+@@ -52,11 +63,18 @@
.brightness_set = a780led_aux_set,
};
return 0;
}
-@@ -64,6 +112,7 @@
+@@ -64,6 +82,7 @@
{
led_classdev_resume(&a780_main_led);
led_classdev_resume(&a780_aux_led);
return 0;
}
#endif
-@@ -77,8 +126,16 @@
+@@ -77,8 +96,16 @@
return ret;
ret = led_classdev_register(&pdev->dev, &a780_aux_led);
return ret;
}
-@@ -87,6 +144,7 @@
+@@ -87,6 +114,7 @@
{
led_classdev_unregister(&a780_main_led);
led_classdev_unregister(&a780_aux_led);
return 0;
}
-@@ -111,6 +169,8 @@
+@@ -111,6 +139,7 @@
{
a780led_main_set( &a780_main_led, 0 );
a780led_aux_set( &a780_aux_led, 0 );
+ a780vibrator_set( &a780_vibrator, 0 );
-+
platform_driver_unregister(&a780led_driver);
}
Index: linux-2.6.21/drivers/leds/Kconfig
===================================================================
---- linux-2.6.21.orig/drivers/leds/Kconfig 2007-05-08 15:09:26.000000000 -0300
-+++ linux-2.6.21/drivers/leds/Kconfig 2007-05-08 15:09:26.000000000 -0300
+--- linux-2.6.21.orig/drivers/leds/Kconfig 2007-09-01 00:15:03.000000000 -0300
++++ linux-2.6.21/drivers/leds/Kconfig 2007-09-01 00:15:08.000000000 -0300
@@ -105,11 +105,11 @@
be configured via sysfs. If unsure, say Y.
--- /dev/null
+Index: linux-2.6.21/sound/soc/pxa/pxa2xx-pcm.c
+===================================================================
+--- linux-2.6.21.orig/sound/soc/pxa/pxa2xx-pcm.c 2007-09-02 22:30:56.000000000 -0300
++++ linux-2.6.21/sound/soc/pxa/pxa2xx-pcm.c 2007-09-02 22:36:26.000000000 -0300
+@@ -153,7 +153,8 @@
+ static int pxa2xx_pcm_prepare(struct snd_pcm_substream *substream)
+ {
+ struct pxa2xx_runtime_data *prtd = substream->runtime->private_data;
+-
++ /* no dma if on loopback */
++ if (!prtd->params) return 0;
+ DCSR(prtd->dma_ch) &= ~DCSR_RUN;
+ DCSR(prtd->dma_ch) = 0;
+ DCMD(prtd->dma_ch) = 0;
Index: linux-2.6.21/sound/soc/pxa/pxa2xx-ssp.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/sound/soc/pxa/pxa2xx-ssp.c 2007-05-14 21:14:38.000000000 -0300
++++ linux-2.6.21/sound/soc/pxa/pxa2xx-ssp.c 2007-09-02 22:50:31.000000000 -0300
@@ -0,0 +1,671 @@
+/*
+ * pxa2xx-ssp.c -- ALSA Soc Audio Layer
+#include "pxa2xx-pcm.h"
+#include "pxa2xx-ssp.h"
+
-+#define PXA_SSP_DEBUG 1
++#define PXA_SSP_DEBUG 0
+
+/*
+ * The following should be defined in pxa-regs.h
Index: linux-2.6.21/sound/soc/pxa/pxa2xx-ssp.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/sound/soc/pxa/pxa2xx-ssp.h 2007-05-14 21:14:38.000000000 -0300
++++ linux-2.6.21/sound/soc/pxa/pxa2xx-ssp.h 2007-09-02 22:48:59.000000000 -0300
@@ -0,0 +1,42 @@
+/*
+ * linux/sound/arm/pxa2xx-ssp.h
+#endif
Index: linux-2.6.21/sound/soc/pxa/Kconfig
===================================================================
---- linux-2.6.21.orig/sound/soc/pxa/Kconfig 2007-05-14 21:16:22.000000000 -0300
-+++ linux-2.6.21/sound/soc/pxa/Kconfig 2007-05-14 21:17:01.000000000 -0300
+--- linux-2.6.21.orig/sound/soc/pxa/Kconfig 2007-09-02 22:48:51.000000000 -0300
++++ linux-2.6.21/sound/soc/pxa/Kconfig 2007-09-02 22:50:18.000000000 -0300
@@ -20,6 +20,10 @@
config SND_PXA2XX_SOC_I2S
tristate
depends on SND_PXA2XX_SOC && PXA_SHARP_C7xx
Index: linux-2.6.21/sound/soc/pxa/Makefile
===================================================================
---- linux-2.6.21.orig/sound/soc/pxa/Makefile 2007-05-14 21:14:52.000000000 -0300
-+++ linux-2.6.21/sound/soc/pxa/Makefile 2007-05-14 21:16:10.000000000 -0300
+--- linux-2.6.21.orig/sound/soc/pxa/Makefile 2007-09-02 22:48:51.000000000 -0300
++++ linux-2.6.21/sound/soc/pxa/Makefile 2007-09-02 22:50:18.000000000 -0300
@@ -2,10 +2,12 @@
snd-soc-pxa2xx-objs := pxa2xx-pcm.o
snd-soc-pxa2xx-ac97-objs := pxa2xx-ac97.o
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-08-01 19:53:13.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-08-01 19:55:54.000000000 -0300
-@@ -222,8 +222,33 @@
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-09-06 00:47:32.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-09-06 00:48:06.000000000 -0300
+@@ -214,8 +214,33 @@
},
};
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-08-01 19:55:54.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-08-01 19:56:21.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-09-07 11:07:33.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-09-07 11:10:47.000000000 -0300
@@ -15,6 +15,7 @@
#include <linux/fb.h>
#include <linux/mmc/host.h>
#ifdef CONFIG_EZX_PCAP
extern int ezx_pcap_mmcsd_power(int);
-@@ -246,6 +249,58 @@
+@@ -238,6 +241,58 @@
.resource = e680_emu_resources,
};
static struct platform_device *devices[] __initdata = {
&e680_pcap_device,
&e680_emu_device,
-@@ -266,6 +321,7 @@
+@@ -258,6 +313,7 @@
set_pxa_fb_info(&e680_fb_info);
pxa_set_mci_info(&e680_mci_platform_data);
Index: linux-2.6.21/drivers/leds/Kconfig
===================================================================
---- linux-2.6.21.orig/drivers/leds/Kconfig 2007-08-01 20:03:29.000000000 -0300
-+++ linux-2.6.21/drivers/leds/Kconfig 2007-08-01 20:04:02.000000000 -0300
+--- linux-2.6.21.orig/drivers/leds/Kconfig 2007-09-06 00:49:29.000000000 -0300
++++ linux-2.6.21/drivers/leds/Kconfig 2007-09-06 00:51:36.000000000 -0300
@@ -111,6 +111,13 @@
This option enables support for the LEDs on the
Motorola A780 GSM Phone.
depends on LEDS_TRIGGERS
Index: linux-2.6.21/drivers/leds/Makefile
===================================================================
---- linux-2.6.21.orig/drivers/leds/Makefile 2007-08-01 20:03:29.000000000 -0300
-+++ linux-2.6.21/drivers/leds/Makefile 2007-08-01 20:04:02.000000000 -0300
+--- linux-2.6.21.orig/drivers/leds/Makefile 2007-09-06 00:49:29.000000000 -0300
++++ linux-2.6.21/drivers/leds/Makefile 2007-09-06 00:49:30.000000000 -0300
@@ -17,6 +17,7 @@
obj-$(CONFIG_LEDS_H1940) += leds-h1940.o
obj-$(CONFIG_LEDS_COBALT) += leds-cobalt.o
Index: linux-2.6.21/drivers/leds/leds-e680.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/drivers/leds/leds-e680.c 2007-08-01 20:04:02.000000000 -0300
++++ linux-2.6.21/drivers/leds/leds-e680.c 2007-09-06 00:51:22.000000000 -0300
@@ -0,0 +1,235 @@
+/*
+ * EZX Platform LED Driver for the Motorola E680(i) GSM Phone
+ ledr_i = led_register_value[color].pcap_LEDR_I;
+ ledg_i = led_register_value[color].pcap_LEDG_I;
+
-+ ezx_pcap_read(SSP_PCAP_ADJ_PERIPH_REGISTER,&tempValue);
++ ezx_pcap_read(PCAP_REG_PERIPH,&tempValue);
+
+ tempValue &= (~SSP_PCAP_LED_MASK);
+
+ (ledg_ctrl << 6) | (ledr_i << 10) | (ledg_i << 12) |
+ (skip << 14)) & 0x7fff) << SSP_PCAP_LED_SHIFT;
+
-+ ezx_pcap_write(SSP_PCAP_ADJ_PERIPH_REGISTER,tempValue);
++ ezx_pcap_write(PCAP_REG_PERIPH,tempValue);
+}
+
+static void e680led_keypad_set(struct led_classdev *led_cdev, enum led_brightness value)
+MODULE_LICENSE("GPL");
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-08-01 20:02:32.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-08-01 20:04:02.000000000 -0300
-@@ -347,11 +347,20 @@
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-09-06 00:49:23.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-09-06 00:49:30.000000000 -0300
+@@ -339,11 +339,20 @@
},
};
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-08-01 19:58:54.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-08-01 20:02:32.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-09-06 00:48:32.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-09-06 00:49:23.000000000 -0300
@@ -16,6 +16,7 @@
#include <linux/mmc/host.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-@@ -325,10 +326,32 @@
+@@ -317,10 +318,32 @@
.resource = pcap_ts_resources,
};
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-06-28 22:45:27.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-06-28 22:53:10.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-09-07 11:32:30.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-09-07 11:54:44.000000000 -0300
@@ -13,6 +13,8 @@
#include <linux/init.h>
#include <linux/platform_device.h>
static struct pxafb_mode_info mode_e680 = {
.pixclock = 150000,
.xres = 240,
-@@ -144,6 +240,7 @@
+@@ -136,6 +232,7 @@
PSLR = 0x05800f00;
set_pxa_fb_info(&e680_fb_info);
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-06-28 22:44:12.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-06-28 22:45:27.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-09-06 00:41:38.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-09-06 00:44:56.000000000 -0300
@@ -19,6 +19,7 @@
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxafb.h>
#include "generic.h"
-@@ -48,7 +49,85 @@
+@@ -48,7 +49,77 @@
.pxafb_lcd_power = &ezx_lcd_power,
};
+static int __init e680_pcap_init(void)
+{
+ /* initialize PCAP registers */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1CTRL, 1);
-+// ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL3);
-+
+ /* set SW1 sleep to keep SW1 1.3v in sync mode */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE10, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE11, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE10, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE11, 0);
+
+ /* SW1 active in sync mode */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE00, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE01, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE00, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE01, 0);
+
+ /* at SW1 -core voltage to 1.30V */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW10_DVS, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW11_DVS, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW12_DVS, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW13_DVS, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW10_DVS, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW11_DVS, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW12_DVS, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW13_DVS, 0);
+
+ /* when STANDY2 PIN ACTIVE (high) set V3-- sram V8 -- pll off */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_LOWPWR, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_LOWPWR, 0);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V3_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V3_LOWPWR, 0);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V8_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V8_LOWPWR, 0);
+
+ /*
+ * when STANDY2 PIN ACTIVE (high) set V4-- lcd only for e680 V6 ---
+ * camera for e680
+ */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_LOWPWR, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_LOWPWR, 0);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V4_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V4_LOWPWR, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V6_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V6_LOWPWR, 0);
+
+ /* set Vc to low power mode when AP sleep */
-+// SSP_PCAP_bit_set( SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VC_STBY);
-+
-+ /* set VAUX2 to voltage 2.775V and low power mode when AP sleep */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_1, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_0, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_LOWPWR, 1);
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN, 1);
++// SSP_PCAP_bit_set( PCAP_BIT_LOWPWR_CTRL_VC_STBY);
+
-+// PGSR(GPIO34_TXENB) |= GPIO_bit(GPIO34_TXENB);
++ /* set VAUX2 to low power mode when AP sleep */
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_VAUX2_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_VAUX2_LOWPWR, 1);
+
+ return 0;
+}
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-08-01 19:56:21.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-08-01 19:58:54.000000000 -0300
-@@ -301,9 +301,34 @@
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-e680.c 2007-09-07 11:10:47.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-e680.c 2007-09-07 11:11:01.000000000 -0300
+@@ -293,9 +293,34 @@
},
};
Index: linux-2.6.21/sound/soc/codecs/pcap2.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/sound/soc/codecs/pcap2.c 2007-08-04 22:20:36.000000000 -0300
-@@ -0,0 +1,709 @@
++++ linux-2.6.21/sound/soc/codecs/pcap2.c 2007-09-07 14:28:32.000000000 -0300
+@@ -0,0 +1,796 @@
+/*
-+ * pcap2.c -- Template Codec Audio driver
++ * pcap2.c - PCAP2 ASIC Audio driver
++ *
++ * Copyright (C) 2007 Daniel Ribeiro <drwyrm@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+
+extern int ezx_pcap_write(u_int8_t, u_int32_t);
+extern int ezx_pcap_read(u_int8_t, u_int32_t *);
++static struct snd_soc_device *pcap2_codec_socdev;
+
+/*
+ * Debug
+ */
+
-+#define PCAP2_DEBUG 1
++//#define PCAP2_DEBUG
+
+#ifdef PCAP2_DEBUG
+#define dbg(format, arg...) \
+ printk(KERN_DEBUG AUDIO_NAME ": " format "\n" , ## arg)
+#else
-+#define dbg(format, arg...) do {} while (0)
++#define dbg(format, arg...)
+#endif
+
+#define err(format, arg...) \
+
+
+/*
-+ * write to the pcap2 codec register space
++ * ASoC limits register value to 16 bits and pcap uses 32 bit registers
++ * to work around this, we get 16 bits from low, mid or high positions.
++ * ASoC limits register number to 8 bits we use 0x1f for register
++ * number and 0xe0 for register offset. -WM
+ */
+static int pcap2_codec_write(struct snd_soc_codec *codec, unsigned int reg,
+ unsigned int value)
+{
-+ dbg("codec_write reg=%08x, val=%08x", reg, value);
-+ ezx_pcap_write(reg, value);
++ unsigned int tmp;
++
++ ezx_pcap_read((reg & 0x1f), &tmp);
++
++ if (reg & SL) {
++ tmp &= 0xffff0000;
++ tmp |= (value & 0xffff);
++ }
++ else if (reg & SM) {
++ tmp &= 0xff0000ff;
++ tmp |= ((value << 8) & 0x00ffff00);
++ }
++ else if (reg & SH) {
++ tmp &= 0xffff;
++ tmp |= ((value << 16) & 0xffff0000);
++ }
++ else
++ tmp = value;
++
++ dbg("codec_write reg=%x, rval=%08x, fval=%08x", reg, tmp, value);
++ ezx_pcap_write((reg & 0x1f), tmp);
+ return 0;
+
+}
+
+static unsigned int pcap2_codec_read(struct snd_soc_codec *codec, unsigned int reg)
+{
-+ unsigned int ret;
-+
-+ ezx_pcap_read(reg, &ret);
-+ dbg("codec_read reg=%08x, val=%08x", reg, ret);
++ unsigned int tmp, ret;
++
++ ezx_pcap_read((reg & 0x1f), &tmp);
++ ret = tmp;
++ if (reg & SL)
++ ret = (tmp & 0xffff);
++ else if (reg & SM)
++ ret = ((tmp >> 8) & 0xffff);
++ else if (reg & SH)
++ ret = ((tmp >> 16) & 0xffff);
++
++ dbg("codec_read reg=%x, rval=%08x, fval=%08x", reg, tmp, ret);
+ return(ret);
+
+}
+
-+static const char *pcap2_amp_output[] = {"R L Stereo", "RL", "RL3db", "RL6db"};
++static const char *pcap2_output_select[] = {"2ch", "2->1ch", "2->1ch -3db", "2->1ch -6db"};
+
+static const struct soc_enum pcap2_enum[] = {
-+SOC_ENUM_SINGLE(PCAP2_OUTPUT_AMP, 19, 4, pcap2_amp_output),
++SOC_ENUM_SINGLE((PCAP2_OUTPUT_AMP|SH), 3, 4, pcap2_output_select),
++};
++
++static const struct snd_kcontrol_new pcap2_input_mixer_controls[] = {
++SOC_DAPM_SINGLE("A3 Switch", (PCAP2_INPUT_AMP|SL), 6, 1, 0),
++SOC_DAPM_SINGLE("A5 Switch", (PCAP2_INPUT_AMP|SL), 8, 1, 0),
++};
+
++static const struct snd_kcontrol_new pcap2_output_mixer_controls[] = {
++SOC_DAPM_SINGLE("A1 Switch", (PCAP2_OUTPUT_AMP|SL), 0, 1, 0),
++SOC_DAPM_SINGLE("A2 Switch", (PCAP2_OUTPUT_AMP|SL), 1, 1, 0),
++SOC_DAPM_SINGLE("AR Switch", (PCAP2_OUTPUT_AMP|SL), 5, 1, 0),
++SOC_DAPM_SINGLE("AL Switch", (PCAP2_OUTPUT_AMP|SL), 6, 1, 0),
+};
+
+/* pcap2 codec non DAPM controls */
+static const struct snd_kcontrol_new pcap2_codec_snd_controls[] = {
-+SOC_SINGLE("Output gain", PCAP2_OUTPUT_AMP, 13, 15, 0),
-+SOC_SINGLE("Input gain", PCAP2_INPUT_AMP, 0, 31, 0),
-+SOC_SINGLE("louderspeaker sw", PCAP2_OUTPUT_AMP, 1, 1, 0),
-+SOC_SINGLE("Earpiece switch", PCAP2_OUTPUT_AMP, 0, 1, 0),
-+SOC_SINGLE("Earpctrl switch", PCAP2_OUTPUT_AMP, 17, 1, 0),
-+SOC_SINGLE("Aright switch", PCAP2_OUTPUT_AMP, 5, 1, 0),
-+SOC_SINGLE("Aleft switch", PCAP2_OUTPUT_AMP, 6, 1, 0),
-+//SOC_SINGLE("AHS switch", PCAP2_INPUT_AMP, 14, 1, 0),
-+//SOC_SINGLE("pga in switch", PCAP2_OUTPUT_AMP, 10, 1, 0),
-+SOC_ENUM("Output mode", pcap2_enum[0]),
++SOC_SINGLE("Output gain", (PCAP2_OUTPUT_AMP|SM), 5, 15, 0),
++SOC_SINGLE("Input gain", (PCAP2_INPUT_AMP|SL), 0, 31, 0),
++};
++
++static const struct snd_kcontrol_new pcap2_codec_dm_mux_control[] = {
++ SOC_DAPM_ENUM("Output Mode", pcap2_enum[0]),
+};
+
+/* add non dapm controls */
+static int pcap2_codec_add_controls(struct snd_soc_codec *codec)
+{
+ int err, i;
-+ dbg("pcap2_codec_add_controls");
+
+ for (i = 0; i < ARRAY_SIZE(pcap2_codec_snd_controls); i++) {
+ if ((err = snd_ctl_add(codec->card,
+
+/* pcap2 codec DAPM controls */
+static const struct snd_soc_dapm_widget pcap2_codec_dapm_widgets[] = {
++ SND_SOC_DAPM_DAC("ST_DAC", "ST_DAC playback", SND_SOC_NOPM, 0, 0),
++ SND_SOC_DAPM_DAC("CDC_DAC", "CDC_DAC playback", SND_SOC_NOPM, 0, 0),
++ SND_SOC_DAPM_ADC("CDC_ADC", "CDC_DAC capture", SND_SOC_NOPM, 0, 0),
++ SND_SOC_DAPM_PGA("PGA_ST", (PCAP2_OUTPUT_AMP|SL), 9, 0, NULL, 0),
++ SND_SOC_DAPM_PGA("PGA_CDC", (PCAP2_OUTPUT_AMP|SL), 8, 0, NULL, 0),
++ SND_SOC_DAPM_PGA("PGA_R", (PCAP2_OUTPUT_AMP|SL), 11, 0, NULL, 0),
++ SND_SOC_DAPM_PGA("PGA_L", (PCAP2_OUTPUT_AMP|SL), 12, 0, NULL, 0),
++ SND_SOC_DAPM_MUX("Downmixer", SND_SOC_NOPM, 0, 0, pcap2_codec_dm_mux_control),
++ SND_SOC_DAPM_PGA("PGA_A1CTRL", (PCAP2_OUTPUT_AMP|SH), 1, 1, NULL, 0),
++ SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0, &pcap2_output_mixer_controls[0], ARRAY_SIZE(pcap2_output_mixer_controls)),
++ SND_SOC_DAPM_OUTPUT("A1"), /* Earpiece */
++ SND_SOC_DAPM_OUTPUT("A2"), /* LoudSpeaker */
++ SND_SOC_DAPM_OUTPUT("AR"), /* headset right */
++ SND_SOC_DAPM_OUTPUT("AL"), /* headset left */
++
++ SND_SOC_DAPM_MICBIAS("BIAS1", (PCAP2_INPUT_AMP|SL), 10, 0),
++ SND_SOC_DAPM_MICBIAS("BIAS2", (PCAP2_INPUT_AMP|SL), 11, 0),
++ SND_SOC_DAPM_MIXER("Input Mixer", SND_SOC_NOPM, 0, 0, &pcap2_input_mixer_controls[0], ARRAY_SIZE(pcap2_input_mixer_controls)),
++ SND_SOC_DAPM_INPUT("A3"), /* Headset Mic */
++ SND_SOC_DAPM_INPUT("A5"), /* Builtin Mic */
+};
+
-+/*
-+ * template codec audio interconnectiosn between sink and source.
-+ */
+static const char *audio_map[][3] = {
++ { "A1", NULL, "Output Mixer" },
++ { "A2", NULL, "Output Mixer" },
++ { "AR", NULL, "Output Mixer" },
++ { "AL", NULL, "Output Mixer" },
++
++ { "Output Mixer", "A1 Switch", "PGA_A1CTRL" },
++ { "Output Mixer", "A2 Switch", "Downmixer" },
++ { "Output Mixer", "AR Switch", "PGA_R" },
++ { "Output Mixer", "AL Switch", "PGA_L" },
++
++ { "PGA_A1CTRL", NULL, "Downmixer" },
++
++ { "Downmixer", "2->1ch", "PGA_L" },
++ { "Downmixer", "2->1ch", "PGA_R" },
++ { "Downmixer", "2->1ch -3db", "PGA_L" },
++ { "Downmixer", "2->1ch -3db", "PGA_R" },
++ { "Downmixer", "2->1ch -6db", "PGA_L" },
++ { "Downmixer", "2->1ch -6db", "PGA_R" },
++ { "Downmixer", "2ch", "PGA_R" },
++
++ { "PGA_R", NULL, "PGA_ST" },
++ { "PGA_L", NULL, "PGA_ST" },
++ { "PGA_R", NULL, "PGA_CDC" },
++
++ { "PGA_ST", NULL, "ST_DAC" },
++ { "PGA_CDC", NULL, "CDC_DAC" },
++
++ /* input path */
++ { "BIAS1", NULL, "A3" },
++ { "BIAS2", NULL, "A5" },
+
++ { "Input Mixer", "A3 Switch", "BIAS1" },
++ { "Input Mixer", "A5 Switch", "BIAS2" },
++
++ { "PGA_R", NULL, "Input Mixer" },
++
++ { "PGA_CDC", NULL, "PGA_R" },
++ { "CDC_ADC", NULL, "PGA_CDC" },
+
+ /* terminator */
+ {NULL, NULL, NULL},
+static int pcap2_codec_add_widgets(struct snd_soc_codec *codec)
+{
+ int i;
-+ dbg("pcap2_codec_add_widgets");
+
+ for(i = 0; i < ARRAY_SIZE(pcap2_codec_dapm_widgets); i++) {
+ snd_soc_dapm_new_control(codec, &pcap2_codec_dapm_widgets[i]);
+ return 0;
+}
+
-+/*
-+ * Alsa operations
-+ * Only implement the required operations for your platform.
-+ * These operations are specific to the codec only.
-+ */
-+
-+ /*
-+ * Called by ALSA when a PCM substream is opened, private data can be allocated.
-+ */
-+static int pcap2mono_codec_startup(struct snd_pcm_substream *substream)
++static int pcap2_codec_dapm_event(struct snd_soc_codec *codec, int event)
+{
-+ dbg("pcap2 codec startup");
++ unsigned int input = pcap2_codec_read(codec, PCAP2_INPUT_AMP);
+
++ input &= ~PCAP2_INPUT_AMP_LOWPWR;
++
++ switch (event) {
++ case SNDRV_CTL_POWER_D0:
++ case SNDRV_CTL_POWER_D1:
++ case SNDRV_CTL_POWER_D2:
++ case SNDRV_CTL_POWER_D3hot: /* Off, with power */
++ dbg("dapm: ON\n");
++ break;
++ case SNDRV_CTL_POWER_D3cold: /* Off, without power */
++ input |= PCAP2_INPUT_AMP_LOWPWR;
++ dbg("dapm: OFF\n");
++ break;
++ }
++ codec->dapm_state = event;
++ pcap2_codec_write(codec, PCAP2_INPUT_AMP, input);
+ return 0;
+}
+
-+/*
-+ * Called by ALSA when a PCM substream is closed. Private data can be
-+ * freed here.
-+ */
-+static int pcap2mono_codec_shutdown(struct snd_pcm_substream *substream)
++static int pcap2_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_device *socdev = rtd->socdev;
-+ struct snd_soc_codec *codec = socdev->codec;
++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++ struct snd_soc_codec *codec = codec_dai->codec;
++ unsigned int tmp;
+
-+ dbg("pcap2mono codec shutdown");
++ if (codec_dai->id == PCAP2_STEREO_DAI) {
++ tmp = pcap2_codec_read(codec, PCAP2_ST_DAC);
+
-+ pcap2_codec_write(codec, PCAP2_CODEC, 0);
-+ return 0;
-+}
++ tmp &= ~PCAP2_ST_DAC_RATE_MASK;
++ switch(params_rate(params)) {
++ case 8000:
++ break;
++ case 11025:
++ tmp |= PCAP2_ST_DAC_RATE_11025;
++ break;
++ case 12000:
++ tmp |= PCAP2_ST_DAC_RATE_12000;
++ break;
++ case 16000:
++ tmp |= PCAP2_ST_DAC_RATE_16000;
++ break;
++ case 22050:
++ tmp |= PCAP2_ST_DAC_RATE_22050;
++ break;
++ case 24000:
++ tmp |= PCAP2_ST_DAC_RATE_24000;
++ break;
++ case 32000:
++ tmp |= PCAP2_ST_DAC_RATE_32000;
++ break;
++ case 44100:
++ tmp |= PCAP2_ST_DAC_RATE_44100;
++ break;
++ case 48000:
++ tmp |= PCAP2_ST_DAC_RATE_48000;
++ break;
++ default:
++ return -EINVAL;
++ }
++ tmp |= PCAP2_ST_DAC_RESET_DF;
++ pcap2_codec_write(codec, PCAP2_ST_DAC, tmp);
++ }
++ else {
++ tmp = pcap2_codec_read(codec, PCAP2_CODEC);
+
-+/*
-+ * Called by ALSA when the hardware params are set by application. This
-+ * function can also be called multiple times and can allocate buffers
-+ * (using snd_pcm_lib_* ). It's non-atomic.
-+ */
-+static int pcap2mono_codec_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+// u_int32_t tmp;
-+ dbg("pcap2mono_codec_hw_params");
++ tmp &= ~PCAP2_CODEC_RATE_MASK;
++ switch(params_rate(params)) {
++ case 8000:
++ break;
++ case 16000:
++ tmp |= PCAP2_CODEC_RATE_16000;
++ break;
++ default:
++ return -EINVAL;
++ }
++ tmp |= PCAP2_CODEC_RESET_DF;
++ pcap2_codec_write(codec, PCAP2_CODEC, tmp);
++ }
+
+ return 0;
+}
+
-+/*
-+ * Free's resources allocated by hw_params, can be called multiple times
-+ */
-+static int pcap2mono_codec_hw_free(struct snd_pcm_substream *substream)
++static int pcap2_hw_free(struct snd_pcm_substream *substream)
+{
-+ dbg("pcap2mono_codec_hw_free");
-+ return 0;
-+}
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++ struct snd_soc_codec *codec = codec_dai->codec;
++ struct snd_soc_dapm_widget *w;
++ unsigned int tmp;
+
-+static int pcap2_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
-+ int clk_id, unsigned int freq, int dir)
-+{
++ if (codec_dai->id == PCAP2_STEREO_DAI) {
++ snd_soc_dapm_set_endpoint(codec, "ST_DAC", 0);
++ tmp = pcap2_codec_read(codec, PCAP2_ST_DAC);
++ tmp &= ~(PCAP2_ST_DAC_EN | PCAP2_ST_DAC_CLK_EN);
++ pcap2_codec_write(codec, PCAP2_ST_DAC, tmp);
++ }
++ else {
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ snd_soc_dapm_set_endpoint(codec, "CDC_DAC", 0);
++ else
++ snd_soc_dapm_set_endpoint(codec, "CDC_ADC", 0);
++ list_for_each_entry(w, &codec->dapm_widgets, list) {
++ if ((!strcmp(w->name, "CDC_DAC") || !strcmp(w->name, "CDC_ADC")) && w->connected)
++ goto in_use;
++ }
++ tmp = pcap2_codec_read(codec, PCAP2_CODEC);
++ tmp &= ~(PCAP2_CODEC_EN | PCAP2_CODEC_CLK_EN);
++ pcap2_codec_write(codec, PCAP2_CODEC, tmp);
++ }
++in_use:
++ snd_soc_dapm_sync_endpoints(codec);
+
-+ dbg("pcap2 set dai sysclk");
+ return 0;
+}
+
-+static int pcap2_set_dai_pll(struct snd_soc_codec_dai *codec_dai,
-+ int pll_id, unsigned int freq_in, unsigned int freq_out)
++static int pcap2_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
++ int clk_id, unsigned int freq, int dir)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
-+ u_int32_t tmp;
-+
-+ dbg("pcap2 set dai pll");
+
++ unsigned int tmp;
+ if (codec_dai->id == PCAP2_STEREO_DAI) {
+ /* ST_DAC */
-+ dbg("stereo codec not supported yet.");
-+ return -ENODEV;
++
++ tmp = pcap2_codec_read(codec, PCAP2_ST_DAC);
++
++ tmp &= ~PCAP2_ST_DAC_CLKSEL_MASK;
++ switch (clk_id) {
++ case PCAP2_CLK_AP:
++ tmp |= PCAP2_ST_DAC_CLKSEL_AP;
++ break;
++ case PCAP2_CLK_BP:
++ break;
++ default:
++ return -ENODEV;
++ }
++
++ tmp &= ~PCAP2_ST_DAC_CLK_MASK;
++ switch (freq) {
++ case 13000000:
++ break;
++/* case 15M36:
++ tmp |= PCAP2_ST_DAC_CLK_15M36;
++ break;
++ case 16M8:
++ tmp |= PCAP2_ST_DAC_CLK_16M8;
++ break;
++ case 19M44:
++ tmp |= PCAP2_ST_DAC_CLK_19M44;
++ break;
++*/ case 26000000:
++ tmp |= PCAP2_ST_DAC_CLK_26M;
++ break;
++/* case EXT_MCLK:
++ tmp |= PCAP2_ST_DAC_CLK_MCLK;
++ break;
++ case FSYNC:
++ tmp |= PCAP2_ST_DAC_CLK_FSYNC;
++ break;
++ case BITCLK:
++ tmp |= PCAP2_ST_DAC_CLK_BITCLK;
++ break;
++*/ default:
++ return -EINVAL;
++ }
++ pcap2_codec_write(codec, PCAP2_ST_DAC, tmp);
+ }
+ else {
+ /* MONO_DAC */
+ tmp = pcap2_codec_read(codec, PCAP2_CODEC);
+
-+ tmp &= ~0x10000;
-+ switch (pll_id) {
-+ case PCAP2_PLL_AP:
-+ tmp |= 0x10000;
++ tmp &= ~PCAP2_CODEC_CLKSEL_MASK;
++ switch (clk_id) {
++ case PCAP2_CLK_AP:
++ tmp |= PCAP2_CODEC_CLKSEL_AP;
+ break;
-+ case PCAP2_PLL_BP:
++ case PCAP2_CLK_BP:
+ break;
+ default:
+ return -ENODEV;
+ }
+
-+ tmp &= ~0x1c0;
-+ switch (freq_in) {
++ tmp &= ~PCAP2_CODEC_CLK_MASK;
++ switch (freq) {
+ case 13000000:
+ break;
+/* case 15M36:
-+ tmp |= 0x40;
++ tmp |= PCAP2_CODEC_CLK_15M36;
+ break;
+ case 16M8:
-+ tmp |= 0x80;
++ tmp |= PCAP2_CODEC_CLK_16M8;
+ break;
+ case 19M44:
-+ tmp |= 0xc0;
++ tmp |= PCAP2_CODEC_CLK_19M44;
+ break;
+*/ case 26000000:
-+ tmp |= 0x100;
++ tmp |= PCAP2_CODEC_CLK_26M;
+ break;
+ default:
+ return -EINVAL;
+ }
-+
-+
+ pcap2_codec_write(codec, PCAP2_CODEC, tmp);
+ }
+ return 0;
+ unsigned int fmt)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
-+ u_int32_t tmp = 0;
-+
-+ dbg("pcap2_set_dai_fmt");
++ unsigned int tmp = 0;
+
+ if (codec_dai->id == PCAP2_STEREO_DAI) {
+ /* ST_DAC */
-+ dbg("stereo codec not supported yet.");
-+ return -ENODEV;
-+ }
-+ else {
-+ /* MONO_DAC */
+
-+ /* disable ST_DAC */
-+ pcap2_codec_write(codec, PCAP2_ST_DAC, 0);
++ /* disable CODEC */
++ pcap2_codec_write(codec, PCAP2_CODEC, 0);
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBM_CFM:
+ break;
+ case SND_SOC_DAIFMT_CBS_CFS:
-+ tmp |= 0x2;
++ tmp |= 0x1;
+ break;
+ default:
+ return -EINVAL;
+ case SND_SOC_DAIFMT_IB_IF:
+ break;
+ case SND_SOC_DAIFMT_NB_NF:
++ tmp |= 0x60000;
++ break;
++ case SND_SOC_DAIFMT_IB_NF:
++ tmp |= 0x40000;
++ break;
++ case SND_SOC_DAIFMT_NB_IF:
++ tmp |= 0x20000;
++ break;
++ }
++ /* set dai to AP */
++ tmp |= 0x1000;
++
++ /* set BCLK */
++ tmp |= 0x18000;
++
++ pcap2_codec_write(codec, PCAP2_ST_DAC, tmp);
++ }
++ else {
++ /* MONO_DAC */
++
++ /* disable ST_DAC */
++ pcap2_codec_write(codec, PCAP2_ST_DAC, 0);
++
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBM_CFM:
++ break;
++ case SND_SOC_DAIFMT_CBS_CFS:
++ tmp |= 0x2;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_DSP_B:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++ case SND_SOC_DAIFMT_IB_IF:
++ break;
++ case SND_SOC_DAIFMT_NB_NF:
+ tmp |= 0x600;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ /* set dai to AP */
+ tmp |= 0x8000;
+
++ tmp |= 0x5; /* IHF / OHF */
++
+ pcap2_codec_write(codec, PCAP2_CODEC, tmp);
+ }
+ return 0;
+}
+
++static int pcap2_prepare(struct snd_pcm_substream *substream)
++{
+
-+#if 0
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A1_CONFIG, 1);
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AHS_CONFIG, 1);
-+
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK_EN, 0);
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_EN, 0);
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_ST_DAC_SMB_ST_DAC,1);
-+
-+// dbg ("configure pcap to use ap clock");
-+// OSCC |= 0x00000008;
-+// pxa_gpio_mode(AP_13MHZ_OUTPUT_PIN | GPIO_ALT_FN_3_OUT);
-+
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_CLK_IN_SEL, 1);
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_CLK_IN_SEL, 1);
-+
-+
-+
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_V2_EN_2, 1);
-+
-+
-+
-+
-+ /* configure bitclk, pllclock, mode */
-+ ezx_pcap_write(PCAP2_ST_DAC, 0);
-+
-+ tmp = PCAP_CDC_CLK_IN_13M0;
-+ ezx_pcap_write(PCAP2_CODEC, tmp);
-+
-+ /* codec 0=master 1=slave */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_SMB, 0);
-+
-+ /* bitrate 0=8k 1=16k */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_FS_8K_16K, 0);
-+
-+ /* clock source */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_CLK_IN_SEL,1);
-+
-+ /* dai select 0=neptune 1=pxa */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_DIG_AUD_IN,1);
-+
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_AUDIHPF,1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_AUDOHPF,1);
-+
-+ /* clock/frame inv */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_CLK_INV,0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_FS_INV,0);
-+
-+ /*(3) reset digital filter(DF_RESET=1) */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_DF_RESET,1);
-+
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_ADITH,0);
-+
-+ /* (4) enable pcap clk(CDC_CLK_EN=1),enable CODEC(CDC_EN=1) */
-+
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_CD_BYP,0);
-+
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK_EN,1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_EN,1);
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++ struct snd_soc_codec *codec = codec_dai->codec;
++ unsigned int tmp;
++ /* FIXME enable clock only if codec is master */
++ if (codec_dai->id == PCAP2_STEREO_DAI) {
++ snd_soc_dapm_set_endpoint(codec, "ST_DAC", 1);
++ snd_soc_dapm_set_endpoint(codec, "CDC_DAC", 0);
++ snd_soc_dapm_set_endpoint(codec, "CDC_ADC", 0);
++ tmp = pcap2_codec_read(codec, PCAP2_ST_DAC);
++ tmp |= (PCAP2_ST_DAC_EN | PCAP2_ST_DAC_CLK_EN);
++ pcap2_codec_write(codec, PCAP2_ST_DAC, tmp);
++ }
++ else {
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ snd_soc_dapm_set_endpoint(codec, "CDC_DAC", 1);
++ else
++ snd_soc_dapm_set_endpoint(codec, "CDC_ADC", 1);
++ snd_soc_dapm_set_endpoint(codec, "ST_DAC", 0);
++ tmp = pcap2_codec_read(codec, PCAP2_CODEC);
++ tmp |= (PCAP2_CODEC_EN | PCAP2_CODEC_CLK_EN);
++ pcap2_codec_write(codec, PCAP2_CODEC, tmp);
++ }
++ snd_soc_dapm_sync_endpoints(codec);
+ mdelay(1);
-+
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_ST_DAC_SW, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_CDC_SW, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_IN_SW, 0);
-+
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_R_EN, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_L_EN, 0);
-+
-+ /* set default output to louderspeaker while developing */
-+ ezx_pcap_read(SSP_PCAP_ADJ_AUD_RX_AMPS_REGISTER, &tmp);
-+ tmp &= ~SSP_PCAP_MONO_PGA_MASK;
-+ tmp |= PCAP_MONO_PGA_RL;
-+ ezx_pcap_write(SSP_PCAP_ADJ_AUD_RX_AMPS_REGISTER, tmp);
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1CTRL, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A2_EN, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A2_CONFIG, 1);
-+
-+ /* set default input to handset while developing */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_MB_ON1, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A5_EN, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A5_MUX, 1);
-+
-+
-+
++#ifdef PCAP2_DEBUG
+ dump_registers();
-+
-+
-+ return 0;
-+}
-+
+#endif
-+
-+/*
-+ * Starts (Triggers) audio playback or capture.
-+ * Usually only needed for DMA
-+ */
-+static int pcap2mono_codec_trigger(struct snd_pcm_substream *substream, int cmd)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_device *socdev = rtd->socdev;
-+ struct snd_soc_codec *codec = socdev->codec;
-+ u_int32_t tmp;
-+
-+ dbg("pcap2mono_codec_trigger");
-+ tmp = pcap2_codec_read(codec, PCAP2_CODEC);
-+
-+
-+ /* reset digital filter */
-+ tmp |= 0x800;
-+
-+ /* enable codec */
-+ tmp |= 0x1000;
-+
-+ /* enable codec clock */
-+ tmp |= 0x2000;
-+
-+ pcap2_codec_write(codec, PCAP2_CODEC, tmp);
-+
-+ dump_registers();
-+ return 0;
-+}
-+
-+/*
-+ * Called by ALSA when the PCM substream is prepared, can set format, sample
-+ * rate, etc. This function is non atomic and can be called multiple times,
-+ * it can refer to the runtime info.
-+ */
-+static int pcap2mono_codec_prepare(struct snd_pcm_substream *substream)
-+{
-+ dbg("pcap2mono_codec_prepare");
-+ return 0;
-+}
-+
-+/*
-+ * Codec DAPM event handler
-+ * This handles codec level DAPM events
-+ */
-+static int pcap2_codec_dapm_event(struct snd_soc_codec *codec, int event)
-+{
-+ switch (event) {
-+ case SNDRV_CTL_POWER_D0: /* full On */
-+ /* e.g. vref/mid, osc on, */
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIO_LOWPWR, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_V2_EN_2, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_V2_EN_2, 1);
-+ break;
-+ case SNDRV_CTL_POWER_D1: /* partial On */
-+ case SNDRV_CTL_POWER_D2: /* partial On */
-+ break;
-+ case SNDRV_CTL_POWER_D3hot: /* Off, with power */
-+ /* everything off except vref/vmid, */
-+ dbg("power on pcap codec");
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIO_LOWPWR, 0);
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_V2_EN_2, 1);
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_V2_EN_2, 1);
-+ break;
-+ case SNDRV_CTL_POWER_D3cold: /* Off, without power */
-+ /* everything off, dac mute, inactive */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIO_LOWPWR, 1);
-+ break;
-+ }
-+ codec->dapm_state = event;
+ return 0;
+}
+
+{
+ .name = "PCAP2 MONO",
+ .id = 0,
-+ /* playback and capture stream info */
+ .playback = {
-+ .stream_name = "mono playback",
++ .stream_name = "CDC_DAC playback",
+ .channels_min = 1,
+ .channels_max = 1,
+ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ .capture = {
-+ .stream_name = "mono capture",
++ .stream_name = "CDC_DAC capture",
+ .channels_min = 1,
+ .channels_max = 1,
+ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
-+ /* codec operations */
-+ /* alsa PCM operations */
+ .ops = {
-+ .startup = pcap2mono_codec_startup,
-+ .shutdown = pcap2mono_codec_shutdown,
-+ .prepare = pcap2mono_codec_prepare,
-+ .trigger = pcap2mono_codec_trigger,
-+ .hw_params = pcap2mono_codec_hw_params,
-+ .hw_free = pcap2mono_codec_hw_free,},
++ .prepare = pcap2_prepare,
++ .hw_params = pcap2_hw_params,
++ .hw_free = pcap2_hw_free,
++ },
+ .dai_ops = {
+// .digital_mute = pcap2_mute,
+ .set_fmt = pcap2_set_dai_fmt,
-+// .set_clkdiv = pcap2_set_dai_clkdiv,
-+ .set_pll = pcap2_set_dai_pll,
+ .set_sysclk = pcap2_set_dai_sysclk,
+ },
+},
+ .name = "PCAP2 STEREO",
+ .id = 1,
+ .playback = {
-+ .stream_name = "stereo playback",
-+ .channels_min = 2,
++ .stream_name = "ST_DAC playback",
++ .channels_min = 1,
+ .channels_max = 2,
-+ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_44100),
++ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |
++ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |
++ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
++ SNDRV_PCM_RATE_48000),
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,
++ },
++ .capture = { /* FIXME: PCAP support this?? */
++ .stream_name = "ST_DAC capture",
++ .channels_min = 1,
++ .channels_max = 1,
++ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |
++ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |
++ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
++ SNDRV_PCM_RATE_48000),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ .ops = {
-+// .startup = pcap2stereo_codec_startup,
-+// .shutdown = pcap2stereo_codec_shutdown,
-+// .prepare = pcap2stereo_codec_prepare,
-+// .trigger = pcap2stereo_codec_trigger,
-+// .hw_params = pcap2stereo_codec_hw_params,
-+// .hw_free = pcap2stereo_codec_hw_free,
++ .prepare = pcap2_prepare,
++ .hw_params = pcap2_hw_params,
++ .hw_free = pcap2_hw_free,
+ },
+ .dai_ops = {
+// .digital_mute = pcap2_mute,
+ .set_fmt = pcap2_set_dai_fmt,
-+// .set_clkdiv = pcap2_set_dai_clkdiv,
-+ .set_pll = pcap2_set_dai_pll,
+ .set_sysclk = pcap2_set_dai_sysclk,
+ },
+},
+ .name = "PCAP2 BP",
+ .id = 2,
+ .playback = {
-+ .stream_name = "baseband playback",
++ .stream_name = "BP playback",
+ .channels_min = 1,
+ .channels_max = 1,
+ .rates = SNDRV_PCM_RATE_8000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ .ops = {
-+ .startup = pcap2mono_codec_startup,
-+// .shutdown = pcap2mono_codec_shutdown,
-+ .prepare = pcap2mono_codec_prepare,
-+ .trigger = pcap2mono_codec_trigger,
-+ .hw_params = pcap2mono_codec_hw_params,
-+ .hw_free = pcap2mono_codec_hw_free,
++ .prepare = pcap2_prepare,
++ .hw_params = pcap2_hw_params,
++ .hw_free = pcap2_hw_free,
+ },
+ .dai_ops = {
+// .digital_mute = pcap2_mute,
+ .set_fmt = pcap2_set_dai_fmt,
-+// .set_clkdiv = pcap2_set_dai_clkdiv,
-+ .set_pll = pcap2_set_dai_pll,
+ .set_sysclk = pcap2_set_dai_sysclk,
+ },
+},
+static int pcap2_codec_init(struct snd_soc_device *socdev)
+{
+ struct snd_soc_codec *codec = socdev->codec;
-+ int reg, ret = 0;
-+
++ int ret = 0;
++
+ dbg("pcap2_codec_init");
+ codec->name = "PCAP2 Audio";
+ codec->owner = THIS_MODULE;
+ if (ret < 0) {
+ snd_soc_free_pcms(socdev);
+ snd_soc_dapm_free(socdev);
-+ dbg("erro registrando\n");
+ }
+
+ return ret;
+}
+
-+static struct snd_soc_device *pcap2_codec_socdev;
-+
-+
+static int pcap2_codec_probe(struct platform_device *pdev)
+{
+ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+struct snd_soc_codec_device soc_codec_dev_pcap2 = {
+ .probe = pcap2_codec_probe,
+ .remove = pcap2_codec_remove,
-+// .suspend = pcap2_codec_suspend,
-+// .resume = pcap2_codec_resume,
++ .suspend = pcap2_codec_suspend,
++ .resume = pcap2_codec_resume,
+};
+
+EXPORT_SYMBOL_GPL(soc_codec_dev_pcap2);
Index: linux-2.6.21/sound/soc/codecs/pcap2.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/sound/soc/codecs/pcap2.h 2007-08-04 02:06:01.000000000 -0300
-@@ -0,0 +1,31 @@
++++ linux-2.6.21/sound/soc/codecs/pcap2.h 2007-09-07 12:13:49.000000000 -0300
+@@ -0,0 +1,81 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+#ifndef _PCAP2_H
+#define _PCAP2_H
+
-+/* PCAP2 register space */
-+
-+#define PCAP2_OUTPUT_AMP 0x0c
-+#define PCAP2_ST_DAC 0x0d
-+#define PCAP2_INPUT_AMP 0x1a
-+#define PCAP2_CODEC 0x0b
++/* 16 bit reads/writes on pcap registers (ugly workaround) */
++#define SL (1 << 5) /* lower 16 bits */
++#define SM (1 << 6) /* mid 16 bits */
++#define SH (1 << 7) /* higher 16 bits */
+
-+#define PCAP2_MONO_DAI 0
-+#define PCAP2_STEREO_DAI 1
-+#define PCAP2_BP_DAI 2
-+
-+#define PCAP2_PLL_BP 0
-+#define PCAP2_PLL_AP 1
-+
-+//struct template_codec_setup_data {
-+// unsigned short i2c_address;
-+//};
++/* PCAP2 register space */
++#define PCAP2_CODEC 0x0b
++#define PCAP2_OUTPUT_AMP 0x0c
++#define PCAP2_ST_DAC 0x0d
++#define PCAP2_INPUT_AMP 0x1a
++
++#define PCAP2_MONO_DAI 0
++#define PCAP2_STEREO_DAI 1
++#define PCAP2_BP_DAI 2
++
++#define PCAP2_CLK_BP 0
++#define PCAP2_CLK_AP 1
++
++#define PCAP2_CODEC_EN 0x2000
++#define PCAP2_CODEC_CLK_EN 0x1000
++#define PCAP2_CODEC_RESET_DF 0x800
++#define PCAP2_CODEC_RATE_MASK 0x4000
++#define PCAP2_CODEC_RATE_8000 0x0
++#define PCAP2_CODEC_RATE_16000 0x4000
++#define PCAP2_CODEC_CLKSEL_MASK 0x10000
++#define PCAP2_CODEC_CLKSEL_AP 0x10000
++#define PCAP2_CODEC_CLKSEL_BP 0x0
++#define PCAP2_CODEC_CLK_MASK 0x1c0
++#define PCAP2_CODEC_CLK_13M 0x0
++#define PCAP2_CODEC_CLK_15M36 0x40
++#define PCAP2_CODEC_CLK_16M8 0x80
++#define PCAP2_CODEC_CLK_19M44 0xc0
++#define PCAP2_CODEC_CLK_26M 0x100
++
++#define PCAP2_ST_DAC_EN 0x80
++#define PCAP2_ST_DAC_CLK_EN 0x20
++#define PCAP2_ST_DAC_RESET_DF 0x40
++#define PCAP2_ST_DAC_RATE_MASK 0xf00
++#define PCAP2_ST_DAC_RATE_8000 0x0
++#define PCAP2_ST_DAC_RATE_11025 0x100
++#define PCAP2_ST_DAC_RATE_12000 0x200
++#define PCAP2_ST_DAC_RATE_16000 0x300
++#define PCAP2_ST_DAC_RATE_22050 0x400
++#define PCAP2_ST_DAC_RATE_24000 0x500
++#define PCAP2_ST_DAC_RATE_32000 0x600
++#define PCAP2_ST_DAC_RATE_44100 0x700
++#define PCAP2_ST_DAC_RATE_48000 0x800
++#define PCAP2_ST_DAC_CLKSEL_MASK 0x80000
++#define PCAP2_ST_DAC_CLKSEL_AP 0x80000
++#define PCAP2_ST_DAC_CLKSEL_BP 0x0
++#define PCAP2_ST_DAC_CLK_MASK 0x1c
++#define PCAP2_ST_DAC_CLK_13M 0x0
++#define PCAP2_ST_DAC_CLK_15M36 0x4
++#define PCAP2_ST_DAC_CLK_16M8 0x8
++#define PCAP2_ST_DAC_CLK_19M44 0xc
++#define PCAP2_ST_DAC_CLK_26M 0x10
++#define PCAP2_ST_DAC_CLK_MCLK 0x14
++#define PCAP2_ST_DAC_CLK_FSYNC 0x18
++#define PCAP2_ST_DAC_CLK_BITCLK 0x1c
++
++#define PCAP2_INPUT_AMP_LOWPWR 0x80000
++#define PCAP2_INPUT_AMP_V2EN2 0x200000
++
++#define PCAP2_OUTPUT_AMP_PGAR_EN 0x800
++#define PCAP2_OUTPUT_AMP_PGAL_EN 0x1000
++#define PCAP2_OUTPUT_AMP_CDC_SW 0x100
++#define PCAP2_OUTPUT_AMP_ST_DAC_SW 0x200
+
+extern struct snd_soc_codec_dai pcap2_dai[];
+extern struct snd_soc_codec_device soc_codec_dev_pcap2;
+#endif
Index: linux-2.6.21/sound/soc/pxa/Kconfig
===================================================================
---- linux-2.6.21.orig/sound/soc/pxa/Kconfig 2007-08-02 22:58:17.000000000 -0300
-+++ linux-2.6.21/sound/soc/pxa/Kconfig 2007-08-02 22:58:34.000000000 -0300
+--- linux-2.6.21.orig/sound/soc/pxa/Kconfig 2007-09-07 12:13:43.000000000 -0300
++++ linux-2.6.21/sound/soc/pxa/Kconfig 2007-09-07 12:13:49.000000000 -0300
@@ -60,4 +60,13 @@
Say Y if you want to add support for SoC audio on Sharp
Zaurus SL-C6000x models (Tosa).
Index: linux-2.6.21/sound/soc/pxa/ezx.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/sound/soc/pxa/ezx.c 2007-08-04 22:35:25.000000000 -0300
-@@ -0,0 +1,296 @@
++++ linux-2.6.21/sound/soc/pxa/ezx.c 2007-09-07 13:12:24.000000000 -0300
+@@ -0,0 +1,349 @@
+/*
++ * ezx.c - Machine specific code for EZX phones
++ *
++ * Copyright (C) 2007 Daniel Ribeiro <drwyrm@gmail.com>
++ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/hardware.h>
+
++#include <asm/arch/ezx-pcap.h>
++
+#include "../codecs/pcap2.h"
+#include "pxa2xx-pcm.h"
+#include "pxa2xx-ssp.h"
+
+#define GPIO_HW_ATTENUATE_A780 96
++
++static struct snd_soc_codec *control_codec;
++
++static void ezx_ext_control(struct snd_soc_codec *codec)
++{
++ if (ezx_pcap_read_bit(pbit(PCAP_REG_PSTAT, PCAP_IRQ_A1)))
++ snd_soc_dapm_set_endpoint(codec, "Headset", 1);
++ else
++ snd_soc_dapm_set_endpoint(codec, "Headset", 0);
++ if (ezx_pcap_read_bit(pbit(PCAP_REG_PSTAT, PCAP_IRQ_MB2)))
++ snd_soc_dapm_set_endpoint(codec, "External Mic", 1);
++ else
++ snd_soc_dapm_set_endpoint(codec, "External Mic", 0);
++
++ snd_soc_dapm_sync_endpoints(codec);
++}
++
++static irqreturn_t jack_irq(int irq, void *data)
++{
++ ezx_ext_control(control_codec);
++ return IRQ_HANDLED;
++}
++
++
+/*
+ * Alsa operations
+ * Only implement the required operations for your platform.
+ */
+static int ezx_machine_startup(struct snd_pcm_substream *substream)
+{
-+ printk("ezx_machine_startup\n");
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->socdev->codec;
++
++ /* check the jack status at stream startup */
++ ezx_ext_control(codec);
+ return 0;
+}
+
+ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
+ int ret;
+
-+
+ /* set codec DAI configuration */
-+ ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B |
-+ SND_SOC_DAIFMT_IB_IF | SND_SOC_DAIFMT_CBM_CFM);
++ if (codec_dai->id == PCAP2_STEREO_DAI)
++ ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B |
++ SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM);
++ else
++ ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B |
++ SND_SOC_DAIFMT_IB_IF | SND_SOC_DAIFMT_CBM_CFM);
+ if(ret < 0)
+ return ret;
+
-+ /* set PLL source */
-+ ret = codec_dai->dai_ops.set_pll(codec_dai, PCAP2_PLL_AP, 13000000, -1);
++ /* Turn on clock output on CLK_PIO */
++ OSCC |= 0x8;
++
++ /* set clock source */
++ ret = codec_dai->dai_ops.set_sysclk(codec_dai, PCAP2_CLK_AP,
++ 13000000, SND_SOC_CLOCK_IN);
+ if(ret < 0)
+ return ret;
+
+ /* set cpu DAI configuration */
+ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_B |
-+ SND_SOC_DAIFMT_IB_IF | SND_SOC_DAIFMT_CBM_CFM);
++ SND_SOC_DAIFMT_IB_IF | SND_SOC_DAIFMT_CBM_CFM);
+ if (ret < 0)
+ return ret;
+
+ if (ret < 0)
+ return ret;
+
-+ ret = cpu_dai->dai_ops.set_sysclk(cpu_dai,PXA2XX_SSP_CLK_PLL, 0, SND_SOC_CLOCK_IN);
++ ret = cpu_dai->dai_ops.set_sysclk(cpu_dai,PXA2XX_SSP_CLK_EXT,
++ 0, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
-+
++
+ return 0;
+}
+
+ */
+static int ezx_machine_hw_free(struct snd_pcm_substream *substream)
+{
-+
-+ printk("ezx_machine_hw_free\n");
++ OSCC &= ~0x8; /* turn off clock output on CLK_PIO */
+
+ return 0;
+}
+
+static int ezx_machine_prepare(struct snd_pcm_substream *substream)
+{
-+ int timeout = 0;
-+ while(((SSSR_P(3) & SSSR_CSS) != 0) && (timeout++ < 10000000));
-+
-+ if (timeout >= 10000000)
-+ printk("clock sync timeout!\n");
-+ else
-+ printk("clock sync passed %d\n", timeout);
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
+
-+// printk("SSCR0 %x SSCR1 %x SSTO %x SSPSP %x SSSR %x SSACD %x\n",
-+// SSCR0_P(3), SSCR1_P(3),
-+// SSTO_P(3), SSPSP_P(3),
-+// SSSR_P(3), SSACD_P(3));
++ if (codec_dai->id == PCAP2_STEREO_DAI) {
++ /* override pxa2xx-ssp sample size for stereo/network mode */
++ SSCR0_P(cpu_dai->id+1) &= ~(SSCR0_DSS | SSCR0_EDSS);
++ SSCR0_P(cpu_dai->id+1) |= (SSCR0_EDSS | SSCR0_DataSize(16));
++ }
+ return 0;
+}
+
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
-+ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
-+ int ret;
-+ printk("bp_hw_params\n");
++// struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++ int ret = 0;
+ /* set codec DAI configuration */
+ ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B |
+ SND_SOC_DAIFMT_IB_IF | SND_SOC_DAIFMT_CBM_CFM);
+ if(ret < 0)
+ return ret;
+
-+ /* set PLL source */
-+ ret = codec_dai->dai_ops.set_pll(codec_dai, PCAP2_PLL_BP, 13000000, -1);
-+ if(ret < 0)
-+ return ret;
++ /* set clock source */
++ ret = codec_dai->dai_ops.set_sysclk(codec_dai, PCAP2_CLK_BP,
++ 13000000, SND_SOC_CLOCK_IN);
+
-+ /* set cpu DAI configuration */
-+// ret = cpu_dai->dai_ops.set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_B |
-+// SND_SOC_DAIFMT_IB_IF | SND_SOC_DAIFMT_CBM_CFM);
-+// if (ret < 0)
-+// return ret;
-+
-+// ret = cpu_dai->dai_ops.set_tristate(cpu_dai, 0);
-+// if (ret < 0)
-+// return ret;
-+
-+// ret = cpu_dai->dai_ops.set_sysclk(cpu_dai,PXA2XX_SSP_CLK_PLL, 0, SND_SOC_CLOCK_IN);
-+// if (ret < 0)
-+// return ret;
-+
-+ return 0;
++ return ret;
+}
+
++
++
++/* machine dapm widgets */
++static const struct snd_soc_dapm_widget ezx_dapm_widgets[] = {
++ SND_SOC_DAPM_HP("Headset", NULL),
++ SND_SOC_DAPM_SPK("Earpiece", NULL),
++ SND_SOC_DAPM_SPK("Loudspeaker", NULL),
++ SND_SOC_DAPM_MIC("Built-in Mic", NULL),
++ SND_SOC_DAPM_MIC("External Mic", NULL),
++};
++
+/* machine audio map (connections to the codec pins) */
+static const char *audio_map[][3] = {
++ { "Headset", NULL, "AR" },
++ { "Headset", NULL, "AL" },
++ { "Earpiece", NULL, "A1" },
++ { "Loudspeaker", NULL, "A2" },
++
++ { "Built-in Mic", NULL, "A5" },
++ { "External Mic", NULL, "A3" },
+
+ {NULL, NULL, NULL},
+};
+ */
+static int ezx_machine_init(struct snd_soc_codec *codec)
+{
-+ printk("ezx machine init\n");
++ int i;
+ /* mark unused codec pins as NC */
++// snd_soc_dapm_set_endpoint(codec, "FIXME", 0);
++ control_codec = codec;
++
++ /* Add ezx specific controls */
++// for (i = 0; i < ARRAY_SIZE(ezx_controls); i++) {
++// if ((err = snd_ctl_add(codec->card, snd_soc_cnew(&ezx_controls[i], codec, NULL))) < 0)
++// return err;
++// }
++
++ /* Add ezx specific widgets */
++ for(i = 0; i < ARRAY_SIZE(ezx_dapm_widgets); i++) {
++ snd_soc_dapm_new_control(codec, &ezx_dapm_widgets[i]);
++ }
++ /* Set up ezx specific audio path interconnects */
++ for(i = 0; audio_map[i][0] != NULL; i++) {
++ snd_soc_dapm_connect_input(codec, audio_map[i][0], audio_map[i][1], audio_map[i][2]);
++ }
+
-+ /* Add template specific controls */
-+
-+ /* Add template specific widgets */
-+
-+ /* Set up template specific audio path audio_map */
+ /* synchronise subsystem */
+ snd_soc_dapm_sync_endpoints(codec);
+ return 0;
+/* template digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link ezx_dai[] = {
+{
-+ .name = "PCAP2 MONO",
-+ .stream_name = "mono playback",
++ .name = "PCAP2 STEREO",
++ .stream_name = "stereo playback",
+ .cpu_dai = &pxa_ssp_dai[PXA2XX_DAI_SSP3],
-+ .codec_dai = &pcap2_dai[PCAP2_MONO_DAI],
++ .codec_dai = &pcap2_dai[PCAP2_STEREO_DAI],
+ .init = ezx_machine_init,
+ .ops = &ezx_ops,
+},
+{
-+ .name = "PCAP2 STEREO",
-+ .stream_name = "stereo playback",
++ .name = "PCAP2 MONO",
++ .stream_name = "mono playback",
+ .cpu_dai = &pxa_ssp_dai[PXA2XX_DAI_SSP3],
-+ .codec_dai = &pcap2_dai[PCAP2_STEREO_DAI],
-+ .init = ezx_machine_init,
++ .codec_dai = &pcap2_dai[PCAP2_MONO_DAI],
++// .init = ezx_machine_init, /* the stereo call already registered our controls */
+ .ops = &ezx_ops,
+},
+{
+ .num_links = ARRAY_SIZE(ezx_dai),
+};
+
-+/* template audio private data */
-+//static struct codec_priv_setup_data template_codec_setup = {
-+// .i2c_address = 0x1b,
-+//};
-+
+/* template audio subsystem */
+static struct snd_soc_device ezx_snd_devdata = {
+ .machine = &snd_soc_machine_ezx,
+ .platform = &pxa2xx_soc_platform,
+ .codec_dev = &soc_codec_dev_pcap2,
-+// .codec_data = &ezx_pcap2_setup,
+};
+
+static struct platform_device *ezx_snd_device;
+static int __init ezx_init(void)
+{
+ int ret;
-+ printk("soc: ezx_init entered\n");
+ ezx_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!ezx_snd_device)
+ return -ENOMEM;
+
+ if (ret)
+ platform_device_put(ezx_snd_device);
-+
++ /* configure gpio for ssp3 */
+ pxa_gpio_mode(GPIO83_SFRM3_MD); /* SFRM */
+ pxa_gpio_mode(GPIO81_STXD3_MD); /* TXD */
-+ pxa_gpio_mode(52 | GPIO_ALT_FN_2_IN); /* SCLK */
++ pxa_gpio_mode(GPIO52_SCLK3_MD); /* SCLK */
+ pxa_gpio_mode(GPIO89_SRXD3_MD); /* RXD */
+
++ /* configure gpio for ssp2 */
++ pxa_gpio_mode(37 | GPIO_IN); /* SFRM */
++ pxa_gpio_mode(38 | GPIO_IN); /* TXD */
++ pxa_gpio_mode(22 | GPIO_IN); /* SCLK */
++ pxa_gpio_mode(88 | GPIO_IN); /* RXD */
+
+ pxa_gpio_mode(GPIO_HW_ATTENUATE_A780 | GPIO_OUT);
+ pxa_gpio_set_value(GPIO_HW_ATTENUATE_A780, 1);
+
-+
-+
++ /* request jack irq */
++ request_irq(EZX_IRQ_HEADJACK, &jack_irq, SA_INTERRUPT, "headphone jack", NULL);
++ request_irq(EZX_IRQ_MIC, &jack_irq, SA_INTERRUPT, "mic jack", NULL);
+
+ return ret;
+}
+
+static void __exit ezx_exit(void)
+{
++ free_irq(EZX_IRQ_HEADJACK, NULL);
++ free_irq(EZX_IRQ_MIC, NULL);
+ platform_device_unregister(ezx_snd_device);
+}
+
+
Index: linux-2.6.21/sound/soc/codecs/Makefile
===================================================================
---- linux-2.6.21.orig/sound/soc/codecs/Makefile 2007-08-02 22:57:48.000000000 -0300
-+++ linux-2.6.21/sound/soc/codecs/Makefile 2007-08-02 22:58:34.000000000 -0300
+--- linux-2.6.21.orig/sound/soc/codecs/Makefile 2007-09-07 12:13:43.000000000 -0300
++++ linux-2.6.21/sound/soc/codecs/Makefile 2007-09-07 12:13:49.000000000 -0300
@@ -2,8 +2,10 @@
snd-soc-wm8731-objs := wm8731.o
snd-soc-wm8750-objs := wm8750.o
+obj-$(CONFIG_SND_SOC_PCAP2) += snd-soc-pcap2.o
Index: linux-2.6.21/sound/soc/codecs/Kconfig
===================================================================
---- linux-2.6.21.orig/sound/soc/codecs/Kconfig 2007-08-02 22:57:48.000000000 -0300
-+++ linux-2.6.21/sound/soc/codecs/Kconfig 2007-08-02 22:58:34.000000000 -0300
+--- linux-2.6.21.orig/sound/soc/codecs/Kconfig 2007-09-07 12:13:43.000000000 -0300
++++ linux-2.6.21/sound/soc/codecs/Kconfig 2007-09-07 12:13:49.000000000 -0300
@@ -13,3 +13,7 @@
config SND_SOC_WM9712
tristate
+ depends on SND_SOC && EZX_PCAP
Index: linux-2.6.21/sound/soc/pxa/Makefile
===================================================================
---- linux-2.6.21.orig/sound/soc/pxa/Makefile 2007-08-02 22:58:17.000000000 -0300
-+++ linux-2.6.21/sound/soc/pxa/Makefile 2007-08-02 22:58:34.000000000 -0300
+--- linux-2.6.21.orig/sound/soc/pxa/Makefile 2007-09-07 12:13:43.000000000 -0300
++++ linux-2.6.21/sound/soc/pxa/Makefile 2007-09-07 12:13:49.000000000 -0300
@@ -14,9 +14,10 @@
snd-soc-poodle-objs := poodle.o
snd-soc-tosa-objs := tosa.o
obj-$(CONFIG_SND_PXA2XX_SOC_SPITZ) += snd-soc-spitz.o
-
+obj-$(CONFIG_SND_PXA2XX_SOC_EZX) += snd-soc-ezx.o
-Index: linux-2.6.21/sound/soc/pxa/pxa2xx-ssp.c
-===================================================================
---- linux-2.6.21.orig/sound/soc/pxa/pxa2xx-ssp.c 2007-08-02 22:58:17.000000000 -0300
-+++ linux-2.6.21/sound/soc/pxa/pxa2xx-ssp.c 2007-08-02 22:58:34.000000000 -0300
-@@ -440,6 +440,12 @@
- case SND_SOC_DAIFMT_NB_NF:
- SSPSP_P(port) |= SSPSP_SFRMP | SSPSP_FSRT;
- break;
-+ case SND_SOC_DAIFMT_NB_IF:
-+ SSPSP_P(port) |= SSPSP_FSRT;
-+ break;
-+ case SND_SOC_DAIFMT_IB_NF:
-+ SSPSP_P(port) |= SSPSP_SFRMP;
-+ break;
- case SND_SOC_DAIFMT_IB_IF:
- break;
- default:
-Index: linux-2.6.21/sound/soc/pxa/pxa2xx-pcm.c
-===================================================================
---- linux-2.6.21.orig/sound/soc/pxa/pxa2xx-pcm.c 2007-08-02 22:57:48.000000000 -0300
-+++ linux-2.6.21/sound/soc/pxa/pxa2xx-pcm.c 2007-08-04 22:46:02.000000000 -0300
-@@ -61,8 +61,9 @@
-
- dcsr = DCSR(dma_ch);
- DCSR(dma_ch) = dcsr & ~DCSR_STOPIRQEN;
--
-+ printk("dma irq dcsr=%08x ", dcsr);
- if (dcsr & DCSR_ENDINTR) {
-+ printk("endintr\n");
- snd_pcm_period_elapsed(substream);
- } else {
- printk( KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n",
-@@ -106,7 +107,8 @@
- return ret;
- prtd->dma_ch = ret;
- }
--
-+ printk("requested dma channel %d\n", ret);
-+
- snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
- runtime->dma_bytes = totsize;
-
-@@ -153,11 +155,13 @@
- static int pxa2xx_pcm_prepare(struct snd_pcm_substream *substream)
- {
- struct pxa2xx_runtime_data *prtd = substream->runtime->private_data;
--
-+ printk("pcm_prepare channel %d\n", prtd->dma_ch);
- DCSR(prtd->dma_ch) &= ~DCSR_RUN;
- DCSR(prtd->dma_ch) = 0;
- DCMD(prtd->dma_ch) = 0;
-- *prtd->params->drcmr = prtd->dma_ch | DRCMR_MAPVLD;
-+
-+ if (prtd->params)
-+ *prtd->params->drcmr = prtd->dma_ch | DRCMR_MAPVLD;
-
- return 0;
- }
-@@ -190,7 +194,7 @@
- default:
- ret = -EINVAL;
- }
--
-+ printk("pcm_trigger ret%d, cmd%d\n", ret, cmd);
- return ret;
- }
-
Index: linux-2.6.21/arch/arm/mach-pxa/ezx.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx.c 2007-06-28 19:44:46.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx.c 2007-06-28 19:44:52.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx.c 2007-06-29 01:07:18.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx.c 2007-08-16 15:52:21.000000000 -0300
@@ -86,8 +86,40 @@
.init = ezx_ohci_init,
};
static int __init ezx_init(void)
Index: linux-2.6.21/arch/arm/mach-pxa/Kconfig
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/Kconfig 2007-06-28 19:44:29.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/Kconfig 2007-06-28 19:44:52.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/Kconfig 2007-06-29 01:07:18.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/Kconfig 2007-08-16 15:52:20.000000000 -0300
@@ -102,6 +102,9 @@
endchoice
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-bp.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-bp.c 2007-06-28 19:44:52.000000000 -0300
-@@ -0,0 +1,249 @@
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-bp.c 2007-08-16 15:52:43.000000000 -0300
+@@ -0,0 +1,262 @@
+/*
+ * BP handshake code for Motorola EZX phones
+ *
+{
+ if (pxa_gpio_get_value(GPIO_BB_WDI2) == 0) {
+ DEBUGP("BP request poweroff!\n");
-+// pm_power_off();
++ /*
++ * It is correct to power off here, the following line is
++ * commented out because e680 lowers WDI2 when BP is in
++ * flash mode, otherwise WDI2 is used to detect low
++ * battery. You can safely uncomment this line if you are
++ * using this kernel with BP in normal mode.
++ */
++#ifndef CONFIG_PXA_EZX_E680
++ pm_power_off();
++#endif
+ }
+}
+
+ if (!bp_handshake_passed()) {
+ handshake();
+ if (bp_handshake_passed()) {
++ /* FIXME: (test) try to not disable irq_wdi2 and drain battery */
+ disable_irq(bp->irq_wdi2);
+
+ /* set bp_rdy handle for usb ipc */
+static irqreturn_t bp_wdi2_handler(int irq, void *dev_id)
+{
+ DEBUGP("BP request poweroff!\n");
-+// pm_power_off();
++ /* same case as check_power_off() */
++#ifndef CONFIG_PXA_EZX_E680
++ pm_power_off();
++#endif
+ return IRQ_HANDLED;
+}
+
+
Index: linux-2.6.21/arch/arm/mach-pxa/Makefile
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/Makefile 2007-06-28 19:44:29.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/Makefile 2007-06-28 19:44:52.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/Makefile 2007-06-29 01:07:18.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/Makefile 2007-08-16 15:52:20.000000000 -0300
@@ -24,6 +24,7 @@
obj-$(CONFIG_PXA_EZX_E2) += ezx-e2.o
obj-$(CONFIG_PXA_EZX_A1200) += ezx-a1200.o
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-emu.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-emu.c 2007-08-01 19:45:27.000000000 -0300
-@@ -0,0 +1,215 @@
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-emu.c 2007-09-07 15:27:23.000000000 -0300
+@@ -0,0 +1,219 @@
+/*
+ * EMU Driver for Motorola EZX phones
+ *
+static struct pxa2xx_udc_mach_info ezx_udc_info;
+extern int ezx_pcap_bit_set(u_int32_t, u_int8_t);
+extern int ezx_pcap_read_bit(u_int32_t);
++static int emu_irq_usb4v;
++static int emu_irq_usb1v;
++
+
+#if defined CONFIG_EZX_EMU_USB
+#define emu_switch_to_default() emu_switch_to_usb()
+
+void emu_switch_to_usb(void)
+{
++ printk(KERN_NOTICE "EMU: Switching to USB\n");
+ pxa_gpio_mode(GPIO34_USB_P2_2_MD);
+ pxa_gpio_mode(GPIO35_USB_P2_1_MD);
+ pxa_gpio_mode(GPIO36_USB_P2_4_MD);
+ pxa_gpio_mode(GPIO40_USB_P2_5_MD);
+ pxa_gpio_mode(GPIO53_USB_P2_3_MD);
+ UP2OCR = 0x02000000;
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_BUSCTRL_RS232ENB, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_BUSCTRL_FSENB, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_BUSCTRL_VUSB_EN, 1);
++ ezx_pcap_bit_set(PCAP_BIT_BUSCTRL_RS232ENB, 1);
++ ezx_pcap_bit_set(PCAP_BIT_BUSCTRL_FSENB, 0);
++ ezx_pcap_bit_set(PCAP_BIT_BUSCTRL_VUSB_EN, 1);
+ clr_GPIO(GPIO_EMU_MUX1);
+ clr_GPIO(GPIO_EMU_MUX2);
+}
+
+void emu_switch_to_uart(void)
+{
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_BUSCTRL_VUSB_EN,0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_BUSCTRL_RS232ENB, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_BUSCTRL_RS232_DIR, 1);
++ printk(KERN_NOTICE "EMU: Switching to UART\n");
++ ezx_pcap_bit_set(PCAP_BIT_BUSCTRL_VUSB_EN,0);
++ ezx_pcap_bit_set(PCAP_BIT_BUSCTRL_RS232ENB, 0);
++ ezx_pcap_bit_set(PCAP_BIT_BUSCTRL_RS232_DIR, 1);
+ set_GPIO(GPIO39_FFTXD);
+ pxa_gpio_mode(GPIO34_TXENB | GPIO_OUT);
+ set_GPIO(GPIO34_TXENB);
+
+void emu_switch_to_audio(int stereo)
+{
++ printk(KERN_NOTICE "EMU: Switching to audio(%s)\n", (stereo ? "stereo" : "mono"));
+ clr_GPIO(GPIO39_VPOUT);
+ if (stereo) {
+ pxa_gpio_mode(GPIO34_TXENB | GPIO_IN);
+
+void emu_switch_to_nothing(void)
+{
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_BUSCTRL_VUSB_EN, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_BUSCTRL_RS232ENB, 1);
++ printk(KERN_NOTICE "EMU: Switching to disconnected\n");
++ ezx_pcap_bit_set(PCAP_BIT_BUSCTRL_VUSB_EN, 0);
++ ezx_pcap_bit_set(PCAP_BIT_BUSCTRL_RS232ENB, 1);
+ pxa_gpio_mode(GPIO34_TXENB | GPIO_OUT);
+ set_GPIO(GPIO34_TXENB);
+ pxa_gpio_mode(GPIO35_XRXD | GPIO_IN);
+{
+ switch (irq) {
+ case EZX_IRQ_USB4V:
-+ if(ezx_pcap_read_bit(SSP_PCAP_ADJ_BIT_PSTAT_USBDET_4V))
++ if(ezx_pcap_read_bit(pbit(PCAP_REG_PSTAT, PCAP_IRQ_USB4V)))
+ emu_switch_to_default();
+ break;
+ case EZX_IRQ_USB1V:
-+ if(!ezx_pcap_read_bit(SSP_PCAP_ADJ_BIT_PSTAT_USBDET_1V))
++ if(!ezx_pcap_read_bit(pbit(PCAP_REG_PSTAT, PCAP_IRQ_USB1V)))
+ emu_switch_to_nothing();
+ break;
+ }
+ pxa_gpio_mode(GPIO_EMU_MUX1 | GPIO_OUT);
+ pxa_gpio_mode(GPIO_EMU_MUX2 | GPIO_OUT);
+
-+ request_irq(EZX_IRQ_USB4V, &emu_irq, SA_INTERRUPT, "usb 4v", NULL);
-+ request_irq(EZX_IRQ_USB1V, &emu_irq, SA_INTERRUPT, "usb 1v", NULL);
++ emu_irq_usb4v = platform_get_irq(dev, 0);
++ if(emu_irq_usb4v < 0) {
++ printk(KERN_ERR "Unable to get IRQ for USB4V!\n");
++ return emu_irq_usb4v;
++ }
++ emu_irq_usb1v = platform_get_irq(dev, 1);
++ if(emu_irq_usb1v < 0) {
++ printk(KERN_ERR "Unable to get IRQ for USB1V!\n");
++ return emu_irq_usb1v;
++ }
++
++ request_irq(emu_irq_usb4v, &emu_irq, SA_INTERRUPT, "usb 4v", NULL);
++ request_irq(emu_irq_usb1v, &emu_irq, SA_INTERRUPT, "usb 1v", NULL);
+
+ pxa_set_udc_info(&ezx_udc_info);
+
-+ if(ezx_pcap_read_bit(SSP_PCAP_ADJ_BIT_PSTAT_USBDET_4V))
++ if(ezx_pcap_read_bit(pbit(PCAP_REG_PSTAT, PCAP_IRQ_USB4V)))
+ emu_switch_to_default();
+ else
+ emu_switch_to_nothing();
+
+static int ezx_emu_remove(struct platform_device *dev)
+{
-+ free_irq(EZX_IRQ_USB4V, NULL);
-+ free_irq(EZX_IRQ_USB1V, NULL);
-+
-+ return 0;
-+}
-+
-+static int ezx_emu_suspend(struct platform_device *dev, pm_message_t state)
-+{
-+ emu_switch_to_nothing();
-+ return 0;
-+}
++ free_irq(emu_irq_usb4v, NULL);
++ free_irq(emu_irq_usb1v, NULL);
+
-+static int ezx_emu_resume(struct platform_device *dev)
-+{
-+ emu_switch_to_default();
+ return 0;
+}
+
+ switch (cmd) {
+ case PXA2XX_UDC_CMD_DISCONNECT:
+ printk(KERN_NOTICE "USB cmd disconnect\n");
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PU,0);
++ ezx_pcap_bit_set(PCAP_BIT_BUSCTRL_USB_PU,0);
+ udc_connected_status = 0;
+ break;
+ case PXA2XX_UDC_CMD_CONNECT:
+ printk(KERN_NOTICE "USB cmd connect\n");
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PU,1);
++ ezx_pcap_bit_set(PCAP_BIT_BUSCTRL_USB_PU,1);
+ udc_connected_status = 1;
+ break;
+ }
+static struct platform_driver ezxemu_driver = {
+ .probe = ezx_emu_probe,
+ .remove = ezx_emu_remove,
-+ .suspend = ezx_emu_suspend,
-+ .resume = ezx_emu_resume,
+ .driver = {
+ .name = "ezx-emu",
+ .owner = THIS_MODULE,
+MODULE_LICENSE("GPL");
Index: linux-2.6.21/arch/arm/mach-pxa/Kconfig
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/Kconfig 2007-08-01 19:39:02.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/Kconfig 2007-08-01 19:45:27.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/Kconfig 2007-09-07 11:32:26.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/Kconfig 2007-09-07 15:34:08.000000000 -0300
@@ -108,6 +108,28 @@
config EZX_PCAP
bool "PCAP Support"
endmenu
Index: linux-2.6.21/arch/arm/mach-pxa/Makefile
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/Makefile 2007-08-01 19:39:02.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/Makefile 2007-08-01 19:45:27.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/Makefile 2007-09-07 11:32:26.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/Makefile 2007-09-07 15:34:08.000000000 -0300
@@ -26,6 +26,7 @@
obj-$(CONFIG_PXA_EZX_E6) += ezx-e6.o
obj-$(CONFIG_EZX_BP) += ezx-bp.o
--- /dev/null
+Index: linux-2.6.21/arch/arm/mach-pxa/ezx-eoc.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-eoc.c 2007-09-09 13:33:19.000000000 -0300
+@@ -0,0 +1,270 @@
++/*
++ * EZX EOC Driver for Motorola EZX phones
++ *
++ * Copyright (C) 2007 Alex Zhang <celeber2@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/i2c.h>
++#include <linux/platform_device.h>
++
++#include <asm/arch/hardware.h>
++#include <asm/arch/pxa-regs.h>
++#include <asm/arch/ezx.h>
++
++#include "ezx-eoc.h"
++
++#if 1
++#define EOC_DBG printk
++#else
++#define EOC_DBG(x, args...)
++#endif
++
++#define EOC_REG_ADDR_SIZE 1
++#define EOC_REG_DATA_SIZE 3
++
++struct ezx_eoc_platform_data *pdata;
++static int eoc_func = EOC_FUNC_USB_NET;
++static const char eoc_i2c_driver_name[] = "ezx-eoc";
++
++/* Addresses to scan */
++static unsigned short normal_i2c[] = {
++ 0x17, /* Address for version 2.0 and above */
++ // 0x7C, /* Address for versions prior too 2.0 */
++ I2C_CLIENT_END
++};
++
++/* I2C Magic */
++I2C_CLIENT_INSMOD;
++
++static int ezx_eoc_attach_adapter(struct i2c_adapter *adapter);
++static int ezx_eoc_detect(struct i2c_adapter *adapter, int address, int kind);
++static int ezx_eoc_detach_client(struct i2c_client *client);
++
++static struct i2c_client *eoc_i2c_client = NULL;
++
++static struct i2c_driver eoc_i2c_driver = {
++ .driver = {
++ .name = (char *)eoc_i2c_driver_name,
++ },
++ .id = I2C_DRIVERID_EEPROM,
++ .attach_adapter = ezx_eoc_attach_adapter,
++ .detach_client = ezx_eoc_detach_client,
++};
++
++int eoc_reg_read(int reg, unsigned int *reg_value)
++{
++ unsigned char reg_num = reg;
++ unsigned char value[EOC_REG_DATA_SIZE];
++ int retval;
++
++ struct i2c_msg msgs[2] =
++ {
++ { 0, 0, EOC_REG_ADDR_SIZE, ®_num },
++ { 0, I2C_M_RD, EOC_REG_DATA_SIZE, value }
++ };
++
++ /* check if we have initialized */ /*not necessary --WM
++ if (eoc_i2c_client == NULL)
++ {
++ EOC_DBG("eoc_reg_read: not initialized\n");
++ return -EINVAL;
++ }
++*/
++ msgs[0].addr = msgs[1].addr = eoc_i2c_client->addr;
++
++ /* transfer message to client */
++ retval = i2c_transfer(eoc_i2c_client->adapter, msgs, 2);
++ if (retval >= 0)
++ {
++ *reg_value = (value[2] << 0);
++ *reg_value |= (value[1] << 8);
++ *reg_value |= (value[0] << 16);
++ }
++ return retval;
++}
++EXPORT_SYMBOL_GPL(eoc_reg_read);
++
++int eoc_reg_write(int reg, unsigned int reg_value)
++{
++ unsigned char value[EOC_REG_ADDR_SIZE + EOC_REG_DATA_SIZE];
++ int retval;
++
++ /* check if we have initialized */ /*not necessary --WM
++ if (eoc_i2c_client == NULL)
++ {
++ EOC_DBG("eoc_reg_write: not initialized\n");
++ return -EINVAL;
++ }
++*/
++ /* Copy the data into a buffer into the correct format */
++ value[0] = reg;
++ value[1] = (reg_value >> 16) & 0xFF;
++ value[2] = (reg_value >> 8) & 0xFF;
++ value[3] = (reg_value >> 0) & 0xFF;
++
++ /* Write the data to the EOC */
++ retval = i2c_master_send (eoc_i2c_client, value, EOC_REG_ADDR_SIZE + EOC_REG_DATA_SIZE);
++
++ return retval;
++}
++EXPORT_SYMBOL_GPL(eoc_reg_write);
++
++static void eoc_switch_to_usb(void)
++{
++ pxa_gpio_mode(GPIO34_USB_P2_2_MD);
++ pxa_gpio_mode(GPIO35_USB_P2_1_MD);
++ pxa_gpio_mode(GPIO36_USB_P2_4_MD);
++ pxa_gpio_mode(GPIO39_USB_P2_6_MD);
++ pxa_gpio_mode(GPIO40_USB_P2_5_MD);
++ pxa_gpio_mode(GPIO53_USB_P2_3_MD);
++ EOC_DBG("ALEX;*********************************************emu_switch_to_usb;\n");
++}
++
++static void eoc_switch_to_nothing(void)
++{
++ pxa_gpio_mode(GPIO34_TXENB | GPIO_OUT);
++ set_GPIO(GPIO34_TXENB);
++ pxa_gpio_mode(GPIO35_XRXD | GPIO_IN);
++ pxa_gpio_mode(GPIO36_VMOUT | GPIO_IN);
++ pxa_gpio_mode(GPIO39_VPOUT | GPIO_IN);
++ pxa_gpio_mode(GPIO40_VPIN | GPIO_IN);
++ pxa_gpio_mode(GPIO53_VMIN | GPIO_IN);
++}
++
++static void eoc_switch_to_default(void)
++{
++ switch (eoc_func) {
++ case EOC_FUNC_USB_NET:
++ eoc_switch_to_usb();
++ break;
++ case EOC_FUNC_NOTHING:
++ eoc_switch_to_nothing();
++ break;
++ }
++}
++
++
++static int ezx_eoc_attach_adapter(struct i2c_adapter *adapter)
++{
++ return i2c_probe(adapter, &addr_data, ezx_eoc_detect);
++}
++
++/* This function is called by i2c_probe */
++static int ezx_eoc_detect(struct i2c_adapter *adapter, int address, int kind)
++{
++ struct i2c_client *new_client;
++ int err = 0;
++
++ if (!(new_client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL)))
++ return -ENOMEM;
++
++ new_client->addr = address;
++ new_client->adapter = adapter;
++ new_client->driver = &eoc_i2c_driver;
++ new_client->flags = 0;
++ strlcpy(new_client->name, eoc_i2c_driver_name, I2C_NAME_SIZE);
++
++ if ((err = i2c_attach_client(new_client))) {
++ kfree(new_client);
++ return err;
++ }
++
++ eoc_i2c_client = new_client;
++
++ if (pdata && pdata->init) {
++ pdata->init();
++ }
++ else
++ return -EINVAL;
++
++ eoc_switch_to_default();
++
++ return 0;
++}
++
++static int ezx_eoc_detach_client(struct i2c_client *client)
++{
++ int err;
++
++ err = i2c_detach_client(client);
++ if (err)
++ return err;
++
++ return 0;
++}
++
++static int __init ezx_eoc_probe(struct platform_device *dev)
++{
++ int ret;
++
++ pdata = dev->dev.platform_data;
++
++ ret = i2c_add_driver(&eoc_i2c_driver);
++ if (ret != 0)
++ return -EINVAL;
++
++ /*
++ * I think we should save platform_data and call init and eoc_switch
++ * from ezx_eoc_detect, after client is setup.
++ * And there is no need for all the "check if initialised" checks if
++ * you assure that you only call read/write after the client is set.
++ * Probably, this was causing the crash on i2c-core too.
++ * --WM
++ */
++
++ /* FIXME: should set udc_info here -WM */
++ return 0;
++}
++
++static int ezx_eoc_remove(struct platform_device *dev)
++{
++ return i2c_del_driver(&eoc_i2c_driver);
++}
++
++static int ezx_eoc_suspend(struct platform_device *dev, pm_message_t state)
++{
++ eoc_switch_to_nothing();
++ return 0;
++}
++
++static int ezx_eoc_resume(struct platform_device *dev)
++{
++ eoc_switch_to_default();
++ return 0;
++}
++
++static struct platform_driver ezx_eoc_driver = {
++ .probe = ezx_eoc_probe,
++ .remove = ezx_eoc_remove,
++ .suspend = ezx_eoc_suspend,
++ .resume = ezx_eoc_resume,
++ .driver = {
++ .name = "ezx-eoc",
++ .owner = THIS_MODULE,
++ },
++};
++
++int __init ezx_eoc_init(void)
++{
++ return platform_driver_register(&ezx_eoc_driver);
++}
++
++void ezx_eoc_exit(void)
++{
++ return platform_driver_unregister(&ezx_eoc_driver);
++}
++
++MODULE_AUTHOR("Alex Zhang <celeber2@gmail.com>");
++MODULE_DESCRIPTION("EZX EOC I2C driver");
++MODULE_LICENSE("GPL");
++
++/* doesnt module_init work?? -WM */
++/*late_initcall(ezx_eoc_init);*/
++module_init(ezx_eoc_init);
++module_exit(ezx_eoc_exit);
+Index: linux-2.6.21/arch/arm/mach-pxa/ezx-eoc.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-eoc.h 2007-09-07 22:15:52.000000000 -0300
+@@ -0,0 +1,33 @@
++/*
++ * linux/arch/arm/mach-pxa/ezx-eoc.h
++ *
++ * Copyright (C) Alex Zhang <celeber2@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __EZX_EOC_H__
++#define __EZX_EOC_H__
++
++enum {
++ POWER_IC_REG_EOC_INT_STATUS,
++ POWER_IC_REG_EOC_INT_MASK,
++ POWER_IC_REG_EOC_INT_SENSE,
++ POWER_IC_REG_EOC_POWER_CONTROL_0,
++ POWER_IC_REG_EOC_POWER_CONTROL_1,
++ POWER_IC_REG_EOC_CONN_CONTROL,
++ POWER_IC_REG_EOC_NUM
++};
++
++enum {
++ EOC_FUNC_NOTHING,
++ EOC_FUNC_USB_NET,
++};
++
++struct ezx_eoc_platform_data {
++ int (*init)(void);
++};
++
++#endif /* __EZX_EOC_H__ */
+Index: linux-2.6.21/arch/arm/mach-pxa/Kconfig
+===================================================================
+--- linux-2.6.21.orig/arch/arm/mach-pxa/Kconfig 2007-09-07 22:15:52.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/Kconfig 2007-09-07 22:15:52.000000000 -0300
+@@ -108,6 +108,12 @@
+ config EZX_PCAP
+ bool "PCAP Support"
+
++config EZX_EOC
++ tristate "EOC i2c driver of Motorola EZX phones"
++ depends on I2C && EXPERIMENTAL && PXA_EZX_A1200
++ help
++ EOC i2c driver of Motorola EZX phones
++
+ config EZX_EMU
+ bool "Motorola Enchanced Mini Usb"
+ depends on EZX_PCAP
+Index: linux-2.6.21/arch/arm/mach-pxa/Makefile
+===================================================================
+--- linux-2.6.21.orig/arch/arm/mach-pxa/Makefile 2007-09-07 22:15:52.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/Makefile 2007-09-07 22:15:52.000000000 -0300
+@@ -27,6 +27,7 @@
+ obj-$(CONFIG_EZX_BP) += ezx-bp.o
+ obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o
+ obj-$(CONFIG_EZX_EMU) += ezx-emu.o
++obj-$(CONFIG_EZX_EOC) += ezx-eoc.o
+
+ # Support for blinky lights
+ led-y := leds.o
Index: linux-2.6.21/drivers/mtd/maps/Kconfig
===================================================================
---- linux-2.6.21.orig/drivers/mtd/maps/Kconfig 2007-04-26 00:08:32.000000000 -0300
-+++ linux-2.6.21/drivers/mtd/maps/Kconfig 2007-04-26 20:49:33.000000000 -0300
-@@ -595,6 +595,28 @@
+--- linux-2.6.21.orig/drivers/mtd/maps/Kconfig 2007-08-31 22:27:53.000000000 -0300
++++ linux-2.6.21/drivers/mtd/maps/Kconfig 2007-08-31 23:04:18.000000000 -0300
+@@ -595,6 +595,34 @@
help
This enables access to the flash chip on the Sharp SL Series of PDAs.
+config MTD_EZX_A780_ALTERNATE
+ bool "A780/E680 Alternate Mapping for BLOB2"
+
++config MTD_EZX_A1200
++ bool "A1200 Original Mapping"
++
+config MTD_EZX_E2
+ bool "E2 Original Mapping"
+
++config MTD_EZX_E6
++ bool "E6 Original Mapping"
++
+endchoice
+
+endif
depends on MTD
Index: linux-2.6.21/drivers/mtd/maps/Makefile
===================================================================
---- linux-2.6.21.orig/drivers/mtd/maps/Makefile 2007-04-26 00:08:32.000000000 -0300
-+++ linux-2.6.21/drivers/mtd/maps/Makefile 2007-04-26 20:30:30.000000000 -0300
+--- linux-2.6.21.orig/drivers/mtd/maps/Makefile 2007-08-31 22:27:53.000000000 -0300
++++ linux-2.6.21/drivers/mtd/maps/Makefile 2007-08-31 23:04:18.000000000 -0300
@@ -72,3 +72,4 @@
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
Index: linux-2.6.21/drivers/mtd/maps/ezx-flash.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/drivers/mtd/maps/ezx-flash.c 2007-04-26 20:30:30.000000000 -0300
++++ linux-2.6.21/drivers/mtd/maps/ezx-flash.c 2007-08-21 17:03:43.000000000 -0300
@@ -0,0 +1,227 @@
+/*
+ * $Id: $
+ .size = 0x00020000,
+ .offset = 0x00020000,
+ } , {
-+ .name = "Kernel 1",
++ .name = "Moto Kernel",
+ .size = 0x000e0000, // 896KB
+ .offset = 0x00040000,
+ } , {
+ .size = 0x01760000,
+ .offset = 0x00120000,
+ } , {
-+ .name = "Kernel 2",
++ .name = "OpenEZX Kernel",
+ .size = 0x00180000, // 1.5MB
+ .offset = 0x01880000,
+ } , {
-+ .name = "VFM_Filesystem",
++ .name = "ezxlocal",
+ .size = 0x005a0000,
+ .offset = 0x01a00000,
+ } , {
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-pcap.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-pcap.c 2007-08-01 20:14:17.000000000 -0300
-@@ -0,0 +1,498 @@
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-pcap.c 2007-08-31 22:48:16.000000000 -0300
+@@ -0,0 +1,513 @@
+/* Driver for Motorola PCAP2 as present in EZX phones
+ *
+ * This is both a SPI device driver for PCAP itself, as well as
+static struct ssp_dev ezx_ssp_dev;
+static struct ssp_state ezx_ssp_state;
+static struct pcap_platform_data *pcap_data;
++static int pcap_irq;
+
+static unsigned long ezx_ssp_pcap_putget(ulong data)
+{
+
+int ezx_pcap_write(u_int8_t reg_num, u_int32_t value)
+{
-+ value &= SSP_PCAP_REGISTER_VALUE_MASK;
-+ value |= SSP_PCAP_REGISTER_WRITE_OP_BIT
-+ | (reg_num<<SSP_PCAP_REGISTER_ADDRESS_SHIFT);
++ value &= PCAP_REGISTER_VALUE_MASK;
++ value |= PCAP_REGISTER_WRITE_OP_BIT
++ | (reg_num<<PCAP_REGISTER_ADDRESS_SHIFT);
+
-+ local_irq_disable();
+ ezx_ssp_pcap_putget(value);
-+ local_irq_enable();
+
+ DEBUGP("pcap write r%x: 0x%08x\n", reg_num, value);
+ return 0;
+
+int ezx_pcap_read(u_int8_t reg_num, u_int32_t *value)
+{
-+ u_int32_t frame = SSP_PCAP_REGISTER_READ_OP_BIT
-+ | (reg_num<<SSP_PCAP_REGISTER_ADDRESS_SHIFT);
++ u_int32_t frame = PCAP_REGISTER_READ_OP_BIT
++ | (reg_num<<PCAP_REGISTER_ADDRESS_SHIFT);
+
-+ local_irq_disable();
+ *value = ezx_ssp_pcap_putget(frame);
-+ local_irq_enable();
+
+ DEBUGP("pcap read r%x: 0x%08x\n", reg_num, *value);
+ return 0;
+{
+ int ret;
+ u_int32_t tmp;
-+ u_int32_t bit = (sspPcapBit & SSP_PCAP_REGISTER_VALUE_MASK);
-+ u_int8_t reg_num = (sspPcapBit & SSP_PCAP_REGISTER_ADDRESS_MASK)
-+ >> SSP_PCAP_REGISTER_ADDRESS_SHIFT;
++ u_int32_t bit = (sspPcapBit & PCAP_REGISTER_VALUE_MASK);
++ u_int8_t reg_num = (sspPcapBit & PCAP_REGISTER_ADDRESS_MASK)
++ >> PCAP_REGISTER_ADDRESS_SHIFT;
+
+ ret = ezx_pcap_read(reg_num, &tmp);
+ if (ret < 0)
+{
+ int ret;
+ u_int32_t tmp;
-+ u_int8_t reg_num = (bit & SSP_PCAP_REGISTER_ADDRESS_MASK)
-+ >> SSP_PCAP_REGISTER_ADDRESS_SHIFT;
++ u_int8_t reg_num = (bit & PCAP_REGISTER_ADDRESS_MASK)
++ >> PCAP_REGISTER_ADDRESS_SHIFT;
+
+ ret = ezx_pcap_read(reg_num, &tmp);
+ if (ret < 0)
+ return ret;
+
-+ return tmp & (bit & SSP_PCAP_REGISTER_VALUE_MASK);
++ return tmp & (bit & PCAP_REGISTER_VALUE_MASK);
+}
+EXPORT_SYMBOL_GPL(ezx_pcap_read_bit);
+
+static struct proc_dir_entry *proc_pcap;
+
+char *pcap_registers[] = {
-+ "ISR\t", "MSR\t", "PSTAT\t", NULL, NULL, NULL, "VREG2\t", "VREG\t",
-+ "BATT_DAC", "ADC1\t", "ADC2\t", "AUD_CODEC", "AUD_RX_AMPS",
-+ "AUD_ST_DAC", NULL, NULL, NULL, NULL, NULL, NULL, "BUSCTRL\t",
-+ "PERIPH\t", NULL, NULL, "LOWPWR\t", NULL, "AUD_TX_AMPS", "GP\t",
-+ NULL, NULL, NULL, NULL, NULL
++ "ISR\t", "MSR\t", "PSTAT\t", "INT_SEL\t", "SWCTRL\t", "VREG1\t",
++ "VREG2\t", "VREG\t", "BATT_DAC", "ADC1\t", "ADC2\t", "AUD_CODEC",
++ "RX_AUD_AMPS", "ST_DAC\t", "RTC_TOD\t", "RTC_TODA", "RTC_DAY\t",
++ "RTC_DAYA", "MTRTMR\t", "PWRCTRL\t", "BUSCTRL\t", "PERIPH\t",
++ "AUXVREG_MASK", "VENDOR_REV", "LOWPWR_CTRL", "PERIPH_MASK",
++ "TX_AUD_AMPS", "GP\t",
++ NULL, NULL, NULL, NULL
+};
+
+static int pcap_read_proc(char *page, char **start, off_t off, int count,
+{
+ u_int32_t tmp;
+
-+ ezx_pcap_read(SSP_PCAP_ADJ_AUX_VREG_REGISTER, &tmp);
++ ezx_pcap_read(PCAP_REG_AUXVREG, &tmp);
+
-+ tmp &= (~SSP_PCAP_VIBRATOR_VOLTAGE_LEVEL_MASK);
-+ tmp |= value;
++ tmp &= ~PCAP_AUXVREG_V_VIB_MASK;
++ tmp |= ((value << PCAP_AUXVREG_V_VIB_SHIFT) & PCAP_AUXVREG_V_VIB_MASK);
+
-+ ezx_pcap_write(SSP_PCAP_ADJ_AUX_VREG_REGISTER, tmp);
++ ezx_pcap_write(PCAP_REG_AUXVREG, tmp);
+}
+EXPORT_SYMBOL_GPL(ezx_pcap_vibrator_level);
+
+void ezx_pcap_mmcsd_voltage(u_int32_t bits)
+{
+ unsigned int tmp;
-+ ezx_pcap_read(SSP_PCAP_ADJ_AUX_VREG_REGISTER, &tmp);
++ ezx_pcap_read(PCAP_REG_AUXVREG, &tmp);
+ if (pcap_data->flags & PCAP_MCI_SD) {
-+ tmp &= 0xffffff9f; /* zero all vaux2 bits */
-+ tmp |= (bits & 0x3) << 5;
++ tmp &= ~PCAP_AUXVREG_VAUX2_MASK;
++ tmp |= ((bits << PCAP_AUXVREG_VAUX2_SHIFT) &
++ PCAP_AUXVREG_VAUX2_MASK);
+ }
+ else if (pcap_data->flags & PCAP_MCI_TF) {
-+ tmp &= 0xfffff0ff; /* zero all vaux3 bits */
-+ tmp |= (bits & 0xf) << 8;
++ tmp &= ~PCAP_AUXVREG_VAUX3_MASK;
++ tmp |= ((bits << PCAP_AUXVREG_VAUX3_SHIFT) &
++ PCAP_AUXVREG_VAUX3_MASK);
+ }
-+ ezx_pcap_write(SSP_PCAP_ADJ_AUX_VREG_REGISTER, tmp);
++ ezx_pcap_write(PCAP_REG_AUXVREG, tmp);
+}
+EXPORT_SYMBOL(ezx_pcap_mmcsd_voltage);
+
+{
+ if (on > 0) on = 1;
+ else on = 0;
++
+ if (pcap_data->flags & PCAP_MCI_SD)
-+ return ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN, on);
++ return ezx_pcap_bit_set(PCAP_BIT_AUXVREG_VAUX2_EN, on);
+ else if (pcap_data->flags & PCAP_MCI_TF)
-+ return ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_EN, on);
++ return ezx_pcap_bit_set(PCAP_BIT_AUXVREG_VAUX3_EN, on);
+ else
+ return -ENODEV;
+}
+static unsigned int pcap2irq[] = {
+ [0] = EZX_IRQ_ADCDONE,
+ [1] = EZX_IRQ_TS,
-+ [2] = 0, /* 1HZ */
-+ [3] = 0, /* WH */
-+ [4] = 0, /* WL */
-+ [5] = 0, /* TODA */
++ [2] = EZX_IRQ_1HZ, /* 1HZ */
++ [3] = EZX_IRQ_WH, /* WH */
++ [4] = EZX_IRQ_WL, /* WL */
++ [5] = EZX_IRQ_TODA, /* TODA */
+ [6] = EZX_IRQ_USB4V,
-+ [7] = 0, /* ONOFF */
-+ [8] = 0, /* ONOFF2 */
++ [7] = EZX_IRQ_ONOFF, /* ONOFF */
++ [8] = EZX_IRQ_ONOFF2, /* ONOFF2 */
+ [9] = EZX_IRQ_USB1V,
-+ [10] = 0, /* MOBPORT */
++ [10] = EZX_IRQ_MOBPORT, /* MOBPORT */
+ [11] = EZX_IRQ_MIC,
+ [12] = EZX_IRQ_HEADJACK,
-+ [13] = 0, /* ST */
-+ [14] = 0, /* PC */
-+ [15] = 0, /* WARM */
-+ [16] = 0, /* EOL */
-+ [17] = 0, /* CLK */
-+ [18] = 0, /* SYSRST */
++ [13] = EZX_IRQ_ST, /* ST */
++ [14] = EZX_IRQ_PC, /* PC */
++ [15] = EZX_IRQ_WARM, /* WARM */
++ [16] = EZX_IRQ_EOL, /* EOL */
++ [17] = EZX_IRQ_CLK, /* CLK */
++ [18] = EZX_IRQ_SYSRST, /* SYSRST */
+ [19] = 0,
+ [20] = EZX_IRQ_ADCDONE2,
-+ [21] = 0, /* SOFTRESET */
-+ [22] = 0, /* MNEXB */
++ [21] = EZX_IRQ_SOFTRESET, /* SOFTRESET */
++ [22] = EZX_IRQ_MNEXB, /* MNEXB */
+};
+
+/* Array indexed by IRQ NUMBER, returns PCAP absolute value */
+static unsigned int irq2pcap[] = {
-+ [EZX_IRQ_USB4V] = SSP_PCAP_ADJ_BIT_ISR_USB4VI,
-+ [EZX_IRQ_USB1V] = SSP_PCAP_ADJ_BIT_ISR_USB1VI,
-+ [EZX_IRQ_HEADJACK] = SSP_PCAP_ADJ_BIT_ISR_A1I,
-+ [EZX_IRQ_MIC] = SSP_PCAP_ADJ_BIT_ISR_MB2I,
-+ [EZX_IRQ_ADCDONE] = SSP_PCAP_ADJ_BIT_ISR_ADCDONEI,
-+ [EZX_IRQ_TS] = SSP_PCAP_ADJ_BIT_ISR_TSI,
-+ [EZX_IRQ_ADCDONE2] = SSP_PCAP_ADJ_BIT_ISR_ADCDONE2I,
++ [EZX_IRQ_MNEXB] = PCAP_IRQ_MNEXB,
++ [EZX_IRQ_SOFTRESET] = PCAP_IRQ_SOFTRESET,
++ [EZX_IRQ_SYSRST] = PCAP_IRQ_SYSRST,
++ [EZX_IRQ_CLK] = PCAP_IRQ_CLK,
++ [EZX_IRQ_EOL] = PCAP_IRQ_EOL,
++ [EZX_IRQ_WARM] = PCAP_IRQ_WARM,
++ [EZX_IRQ_PC] = PCAP_IRQ_PC,
++ [EZX_IRQ_ST] = PCAP_IRQ_ST,
++ [EZX_IRQ_MOBPORT] = PCAP_IRQ_MOBPORT,
++ [EZX_IRQ_ONOFF2] = PCAP_IRQ_ONOFF2,
++ [EZX_IRQ_ONOFF] = PCAP_IRQ_ONOFF,
++ [EZX_IRQ_TODA] = PCAP_IRQ_TODA,
++ [EZX_IRQ_WL] = PCAP_IRQ_WL,
++ [EZX_IRQ_WH] = PCAP_IRQ_WH,
++ [EZX_IRQ_1HZ] = PCAP_IRQ_1HZ,
++ [EZX_IRQ_USB4V] = PCAP_IRQ_USB4V,
++ [EZX_IRQ_USB1V] = PCAP_IRQ_USB1V,
++ [EZX_IRQ_HEADJACK] = PCAP_IRQ_A1,
++ [EZX_IRQ_MIC] = PCAP_IRQ_MB2,
++ [EZX_IRQ_TS] = PCAP_IRQ_TS,
++ [EZX_IRQ_ADCDONE] = PCAP_IRQ_ADCDONE,
++ [EZX_IRQ_ADCDONE2] = PCAP_IRQ_ADCDONE2,
+};
+
+static void pcap_ack_irq(unsigned int irq)
+{
+ DEBUGP("pcap_ack_irq: %u\n", irq);
-+ ezx_pcap_write(SSP_PCAP_ADJ_ISR_REGISTER, irq2pcap[irq]);
++ ezx_pcap_write(PCAP_REG_ISR, irq2pcap[irq]);
+}
+
+static void pcap_mask_irq(unsigned int irq)
+{
+ u_int32_t reg;
++ unsigned long flag;
+
++ spin_lock_irqsave(&ezx_ssp_lock, flag);
+ DEBUGP("pcap_mask_irq: %u\n", irq);
-+
-+ /* this needs to be atomic... but we're not on SMP so it is */
-+ ezx_pcap_read(SSP_PCAP_ADJ_MSR_REGISTER, ®);
++ ezx_pcap_read(PCAP_REG_MSR, ®);
+ reg |= irq2pcap[irq];
-+ ezx_pcap_write(SSP_PCAP_ADJ_MSR_REGISTER, reg);
++ ezx_pcap_write(PCAP_REG_MSR, reg);
++ spin_unlock_irqrestore(&ezx_ssp_lock, flag);
+}
+
+static void pcap_unmask_irq(unsigned int irq)
+{
+ u_int32_t tmp;
-+ DEBUGP("pcap_unmask_irq: %u\n", irq);
++ unsigned long flag;
+
-+ /* this needs to be atomic... but we're not on SMP so it is */
-+ ezx_pcap_read(SSP_PCAP_ADJ_MSR_REGISTER, &tmp);
++ spin_lock_irqsave(&ezx_ssp_lock, flag);
++ DEBUGP("pcap_unmask_irq: %u\n", irq);
++ ezx_pcap_read(PCAP_REG_MSR, &tmp);
+ tmp &= ~irq2pcap[irq];
-+ ezx_pcap_write(SSP_PCAP_ADJ_MSR_REGISTER, tmp);
++ ezx_pcap_write(PCAP_REG_MSR, tmp);
++ spin_unlock_irqrestore(&ezx_ssp_lock, flag);
+}
+
+static struct irq_chip pcap_chip = {
+/* handler for interrupt received from PCAP via GPIO */
+static void pcap_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
+{
++ const unsigned int cpu = smp_processor_id();
+ int i;
-+ const unsigned int cpu = smp_processor_id();
-+ u_int32_t reg, mask;
++ u_int32_t isr, msr;
+
+ spin_lock(&desc->lock);
-+
-+ DEBUGP("pcap_irq_demux_handler(%u,,) entered\n", irq);
-+
-+ desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
-+
-+ if (unlikely(desc->status & IRQ_INPROGRESS)) {
-+ DEBUGP("irq busy, masking it off\n");
-+ desc->status |= (IRQ_PENDING | IRQ_MASKED);
++ desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
++ if (unlikely(desc->status & (IRQ_INPROGRESS | IRQ_DISABLED))) {
++ desc->status |= (IRQ_PENDING | IRQ_MASKED);
+ desc->chip->mask(irq);
+ desc->chip->ack(irq);
+ goto out_unlock;
+ }
-+
-+ kstat_cpu(cpu).irqs[irq]++;
++ kstat_cpu(cpu).irqs[irq]++;
+ desc->chip->ack(irq);
+ desc->status |= IRQ_INPROGRESS;
-+
-+ do {
-+ if (unlikely((desc->status &
-+ (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
-+ (IRQ_PENDING | IRQ_MASKED))) {
-+ DEBUGP("dealing with pending IRQ, unmasking\n");
-+ desc->chip->unmask(irq);
++ do {
++ if (unlikely((desc->status &
++ (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
++ (IRQ_PENDING | IRQ_MASKED))) {
++ desc->chip->unmask(irq);
+ desc->status &= ~IRQ_MASKED;
-+ }
-+
++ }
+ desc->status &= ~IRQ_PENDING;
+
-+ ezx_pcap_read(SSP_PCAP_ADJ_ISR_REGISTER, ®);
-+ ezx_pcap_read(SSP_PCAP_ADJ_MSR_REGISTER, &mask);
-+ DEBUGP("pcap_irq_demux_handler: ISR=0x%08x MSR=0x%08x\n", reg, mask);
-+
-+ for (i = ARRAY_SIZE(pcap2irq)-1; i >= 0; i--) {
-+ unsigned int pirq = pcap2irq[i];
-+ if (pirq == 0)
-+ continue;
-+
-+ if ((reg & (1 << i)) && !(mask & (1 << i))) {
-+ struct irq_desc *subdesc;
-+ DEBUGP("found irq %u\n", pirq);
-+ subdesc = irq_desc + pirq;
-+
-+ kstat_cpu(cpu).irqs[pirq]++;
-+ subdesc->chip->ack(pirq);
-+
-+ spin_unlock(&desc->lock);
-+ handle_IRQ_event(pirq, subdesc->action);
-+ spin_lock(&desc->lock);
-+ }
-+ }
-+
-+ } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
++ ezx_pcap_read(PCAP_REG_ISR, &isr);
++ ezx_pcap_read(PCAP_REG_MSR, &msr);
++ for (i = ARRAY_SIZE(pcap2irq)-1; i >= 0; i--) {
++ unsigned int pirq = pcap2irq[i];
++ struct irq_desc *subdesc;
++ if (pirq == 0 || !(isr & irq2pcap[pirq]))
++ continue;
++ subdesc = irq_desc + pirq;
++ if (msr & irq2pcap[pirq])
++ continue;
++ DEBUGP("found irq %u\n", pirq);
++ spin_unlock(&desc->lock);
++ desc_handle_irq(pirq, subdesc);
++ spin_lock(&desc->lock);
++ }
+
-+ desc->status &= ~IRQ_INPROGRESS;
++ } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
+
++ desc->status &= ~IRQ_INPROGRESS;
+out_unlock:
+ spin_unlock(&desc->lock);
+}
+ int irq;
+ DEBUGP("exz_pcap_remove entered\n");
+
-+ set_irq_chained_handler(IRQ_GPIO1, NULL);
++ set_irq_chained_handler(pcap_irq, NULL);
+
-+ for (irq = EZX_IRQ(0); irq <= EZX_IRQ(6); irq++) {
++ for (irq = EZX_IRQ(0); irq <= EZX_IRQ(21); irq++) {
+ set_irq_chip(irq, NULL);
+ set_irq_handler(irq, NULL);
+ set_irq_flags(irq, 0);
+ pxa_gpio_mode(pcap_data->cs | GPIO_OUT
+ | GPIO_DFLT_HIGH);
+ }
++ pcap_irq = platform_get_irq(pdev, 0);
++ if(pcap_irq < 0) {
++ printk(KERN_ERR "Unable to get IRQ for pcap!\n");
++ return pcap_irq;
++ }
+
+ ret = ssp_init(&ezx_ssp_dev, pcap_data->port, 0);
+ if (ret) {
+ ssp_enable(&ezx_ssp_dev);
+
+ /* mask/ack all PCAP interrupts */
-+ ezx_pcap_write(SSP_PCAP_ADJ_MSR_REGISTER, PCAP_MASK_ALL_INTERRUPT);
-+ ezx_pcap_write(SSP_PCAP_ADJ_ISR_REGISTER, PCAP_CLEAR_INTERRUPT_REGISTER);
++ ezx_pcap_write(PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
++ ezx_pcap_write(PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
+
+ if (pcap_data->init)
+ pcap_data->init();
+
+ /* set up interrupt demultiplexing code for PCAP2 irqs */
-+ set_irq_type(IRQ_GPIO1, IRQT_RISING);
-+ for (irq = EZX_IRQ(0); irq <= EZX_IRQ(6); irq++) {
++ set_irq_type(pcap_irq, IRQT_RISING);
++ for (irq = EZX_IRQ(0); irq <= EZX_IRQ(21); irq++) {
+ set_irq_chip(irq, &pcap_chip);
-+ set_irq_handler(irq, handle_edge_irq);
++ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
-+ set_irq_chained_handler(IRQ_GPIO1, pcap_irq_demux_handler);
++ set_irq_chained_handler(pcap_irq, pcap_irq_demux_handler);
++ set_irq_wake(pcap_irq, 1);
+
+ printk("ezx-pcap: ssp driver registered\n");
+ return ret;
+ DEBUGP("pcap suspend!\n");
+ ssp_flush(&ezx_ssp_dev);
+ ssp_save_state(&ezx_ssp_dev, &ezx_ssp_state);
++ if (pcap_data->cs >= 0)
++ pxa_gpio_mode(pcap_data->cs | GPIO_IN);
+ return 0;
+}
+
+ DEBUGP("pcap resume!\n");
+
+ if (pcap_data->cs >= 0) {
-+ if (pcap_data->flags & PCAP_CS_AH)
++ if (pcap_data->flags & PCAP_CS_AH) {
++ pxa_gpio_mode(pcap_data->cs | GPIO_OUT);
+ GPCR(pcap_data->cs) = GPIO_bit(pcap_data->cs);
-+ else
++ }
++ else {
++ pxa_gpio_mode(pcap_data->cs | GPIO_OUT | GPIO_DFLT_HIGH);
+ GPSR(pcap_data->cs) = GPIO_bit(pcap_data->cs);
++ }
+ }
+ ssp_restore_state(&ezx_ssp_dev,&ezx_ssp_state);
+ ssp_enable(&ezx_ssp_dev);
+
-+ /* ack all irqs */
-+ ezx_pcap_write(SSP_PCAP_ADJ_ISR_REGISTER, PCAP_CLEAR_INTERRUPT_REGISTER);
++ ezx_pcap_write(PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
++
+ return 0;
+}
+
Index: linux-2.6.21/include/asm-arm/arch-pxa/ezx-pcap.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/include/asm-arm/arch-pxa/ezx-pcap.h 2007-06-29 01:07:18.000000000 -0300
-@@ -0,0 +1,678 @@
-+struct pcap_platform_data {
-+ int port;
-+ int cs;
-+ int clk;
-+ int flags;
-+ int (*init)(void);
-+};
-+
-+#define PCAP_CS_AH 0x1
-+#define PCAP_MCI_SD 0x2
-+#define PCAP_MCI_TF 0x4
-+
-+
-+/* (c) Copyright Motorola Beijing 2002 all rights reserved.
-+
-+ Project Name : EZX
-+ Project No. :
-+ Title :
-+ File Name :
-+ Description :
-+
-+ ************** REVISION HISTORY **********************************************
-+ Date Author Reference
-+ ======== ========== ==========================
-+ 2002-07-01 weiqiang lin create
-+*/
-+#ifndef SSP_PCAP_H
-+#define SSP_PCAP_H
-+
-+#define SSP_vibrate_start_command() SSP_PCAP_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN); \
-+ SSP_PCAP_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN)
-+
-+#define SSP_vibrate_stop_command() SSP_PCAP_bit_clean(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN); \
-+ SSP_PCAP_bit_clean(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN)
-+
-+#define SSP_PCAP_REGISTER_VALUE_LENGTH 16
-+
-+#define SSP_PCAP_REGISTER_WRITE_OP_BIT 0x80000000
-+#define SSP_PCAP_REGISTER_READ_OP_BIT 0x00000000
-+
-+#define SSP_PCAP_REGISTER_VALUE_UP_WORD_MASK 0xffff0000
-+#define SSP_PCAP_REGISTER_VALUE_DOWN_WORD_MASK 0x0000ffff
-+
-+#define SSP_PCAP_REGISTER_VALUE_MASK 0x01ffffff
-+#define SSP_PCAP_REGISTER_VALUE_MASK 0x01ffffff
-+#define SSP_PCAP_REGISTER_ADDRESS_MASK 0x7c000000
-+#define SSP_PCAP_REGISTER_ADDRESS_SHIFT 26
-+#define SSP_PCAP_REGISTER_NUMBER 32
-+
-+#define SSP_PCAP_ADC_START_VALUE_SET_MASK 0xfffffc00
-+#define SSP_PCAP_ADC_START_VALUE 0x000001dd
-+
-+
-+#define SSP_PCAP_PHONE_CDC_CLOCK_MASK 0x000001c0
-+#define SSP_PCAP_STEREO_SAMPLE_RATE_MASK 0x00000f00
-+#define SSP_PCAP_STEREO_BCLK_TIME_SLOT_MASK 0x00018000
-+#define SSP_PCAP_STEREO_CLOCK_MASK 0x0000001c
-+#define SSP_PCAP_DIGITAL_AUDIO_MODE_MASK 0x00006000
-+#define SSP_PCAP_TOUCH_PANEL_POSITION_DETECT_MODE_MASK 0x000e0000
-+#define SSP_PCAP_MONO_PGA_MASK 0x00180000
-+
-+#define SSP_PCAP_VIBRATOR_VOLTAGE_LEVEL_MASK 0x00300000
-+
-+#define SSP_PCAP_AUDIO_IN_GAIN_MASK 0x0000001f
-+#define SSP_PCAP_AUDIO_IN_GAIN_SHIFT 0
-+#define SSP_PCAP_AUDIO_OUT_GAIN_MASK 0x0001e000
-+#define SSP_PCAP_AUDIO_OUT_GAIN_SHIFT 13
-+
-+
-+#define SSP_PCAP_ADD1_VALUE_MASK 0x000003ff
-+#define SSP_PCAP_ADD1_VALUE_SHIFT 0
-+#define SSP_PCAP_ADD2_VALUE_MASK 0x000ffc00
-+#define SSP_PCAP_ADD2_VALUE_SHIFT 10
-+
-+
-+#define PCAP_AUDIO_IN_GAIN_MAX_VALUE 31
-+#define PCAP_AUDIO_OUT_GAIN_MAX_VALUE 15
-+
-+#define PCAP_CLEAR_INTERRUPT_REGISTER 0x00141fdf
-+#define PCAP_MASK_ALL_INTERRUPT 0x0013ffff
-+
-+#define SSP_PCAP_TS_KEEPER_TIMER 100 /* 1 second */
-+#define START_ADC_DELAY_TIMER 1991 /* 540 us */
++++ linux-2.6.21/include/asm-arm/arch-pxa/ezx-pcap.h 2007-09-04 23:34:19.000000000 -0300
+@@ -0,0 +1,247 @@
++/*
++ * Copyright 2007 Daniel Ribeiro <drwyrm@gmail.com>
++ */
+
-+#define SSP_SEND_PM_ALART_INTERVAL 1000 *HZ/1000 /* 1 second */
-+#define SSP_SEND_MSG_USB_ACCESSORY_INFO_DEBOUNCE 200 *HZ/1000 /* 200ms */
++#ifndef EZX_PCAP_H
++#define EZX_PCAP_H
+
-+struct ssp_interrupt_info
-+{
-+ u32 type;
-+ u32 status;
-+ void* privdata;
++struct pcap_platform_data {
++ int port; /* SSP port */
++ int cs; /* CS gpio */
++ int clk;
++ int flags; /* driver flags */
++ int (*init)(void); /* board specific driver init */
+};
+
-+#ifndef U8
-+#define U8 unsigned char
-+#endif
-+
-+#ifndef U32
-+#define U32 unsigned long
-+#endif
-+
-+#ifndef U16
-+#define U16 unsigned short
-+#endif
-+
-+#ifndef P_U16
-+#define P_U16 U16*
-+#endif
-+
-+#ifndef P_U32
-+#define P_U32 U32*
-+#endif
-+
-+#define SSP_SELECT_BUFFER (volatile unsigned long *)(0xf4000000)
-+
-+#define SSP_SR_RNE 0x00000008
-+#define SSP_PCAP_BASE 0x00001000
-+/************************ STRUCTURES, ENUMS, AND TYPEDEFS **************************/
-+typedef enum accessoryStatus
-+{
-+ ACCESSORY_DEVICE_STATUS_DETACHED = 0,
-+ ACCESSORY_DEVICE_STATUS_ATTACHED ,
-+ ACCESSORY_DEVICE_STATUS_UNKNOW =0x000000ff
-+}ACCESSORY_DEVICE_STATUS;
-+
-+typedef enum accessoryType
-+{
-+ ACCESSORY_DEVICE_NONE = 0,
-+ ACCESSORY_DEVICE_SERIAL_PORT ,
-+ ACCESSORY_DEVICE_USB_PORT ,
-+ ACCESSORY_DEVICE_UNKNOW =0x000000ff
-+}ACCESSORY_TYPE;
-+
-+typedef enum pcapReturnStatus
-+{
-+ SSP_PCAP_SUCCESS = 0,
-+ SSP_PCAP_ERROR_REGISTER = SSP_PCAP_BASE+1,
-+ SSP_PCAP_ERROR_VALUE = SSP_PCAP_BASE+2,
-+
-+ SSP_PCAP_NOT_RUN = SSP_PCAP_BASE+0xff
-+}SSP_PCAP_STATUS;
-+
-+typedef enum pcapPortType
-+{
-+ SSP_PCAP_SERIAL_PORT = 0x00000000,
-+ SSP_PCAP_LOW_USB_PORT = 0x00000001,
-+ SSP_PCAP_HIGH_USB_PORT = 0x00000002,
-+ SSP_PCAP_UNKNOW_PORT = 0x000000ff
-+}SSP_PCAP_PORT_TYPE;
-+
-+typedef enum pcapInitDriverType
-+{
-+ SSP_PCAP_TS_OPEN = 0x00000000,
-+ SSP_PCAP_AUDIO_OPEN = 0x00000001,
-+ SSP_PCAP_UNKNOW_DRIVER_OPEN = 0x000000ff
-+}SSP_PCAP_INIT_DRIVER_TYPE;
-+
-+
-+typedef enum pcapReturnBitStatus
-+{
-+ SSP_PCAP_BIT_ZERO = 0x00000000,
-+ SSP_PCAP_BIT_ONE = 0x00000001,
-+ SSP_PCAP_BIT_ERROR = 0xff000000
-+}SSP_PCAP_BIT_STATUS;
-+
-+typedef enum pcapCDCClkType
-+{
-+ PCAP_CDC_CLK_IN_13M0 = 0x00000000,
-+ PCAP_CDC_CLK_IN_15M36 = 0x00000040,
-+ PCAP_CDC_CLK_IN_16M8 = 0x00000080,
-+ PCAP_CDC_CLK_IN_19M44 = 0x000000c0,
-+ PCAP_CDC_CLK_IN_26M0 = 0x00000100
-+}PHONE_CDC_CLOCK_TYPE;
-+
-+typedef enum pcapST_SR
-+{
-+ PCAP_ST_SAMPLE_RATE_8K = 0x00000000,
-+ PCAP_ST_SAMPLE_RATE_11K = 0x00000100,
-+ PCAP_ST_SAMPLE_RATE_12K = 0x00000200,
-+ PCAP_ST_SAMPLE_RATE_16K = 0x00000300,
-+ PCAP_ST_SAMPLE_RATE_22K = 0x00000400,
-+ PCAP_ST_SAMPLE_RATE_24K = 0x00000500,
-+ PCAP_ST_SAMPLE_RATE_32K = 0x00000600,
-+ PCAP_ST_SAMPLE_RATE_44K = 0x00000700,
-+ PCAP_ST_SAMPLE_RATE_48K = 0x00000800
-+}ST_SAMPLE_RATE_TYPE;
-+
-+typedef enum pcapST_BCLK
-+{
-+ PCAP_ST_BCLK_SLOT_16 = 0x00000000,
-+ PCAP_ST_BCLK_SLOT_8 = 0x00008000,
-+ PCAP_ST_BCLK_SLOT_4 = 0x00010000,
-+ PCAP_ST_BCLK_SLOT_2 = 0x00018000,
-+}ST_BCLK_TIME_SLOT_TYPE;
-+
-+typedef enum pcapST_CLK
-+{
-+ PCAP_ST_CLK_PLL_CLK_IN_13M0 = 0x00000000,
-+ PCAP_ST_CLK_PLL_CLK_IN_15M36 = 0x00000004,
-+ PCAP_ST_CLK_PLL_CLK_IN_16M8 = 0x00000008,
-+ PCAP_ST_CLK_PLL_CLK_IN_19M44 = 0x0000000c,
-+ PCAP_ST_CLK_PLL_CLK_IN_26M0 = 0x00000010,
-+ PCAP_ST_CLK_PLL_CLK_IN_EXT_MCLK = 0x00000014,
-+ PCAP_ST_CLK_PLL_CLK_IN_FSYNC = 0x00000018,
-+ PCAP_ST_CLK_PLL_CLK_IN_BITCLK = 0x0000001c
-+}ST_CLK_TYPE;
-+
-+typedef enum pcapDigitalAudioInterfaceMode
-+{
-+ PCAP_DIGITAL_AUDIO_INTERFACE_NORMAL = 0x00000000,
-+ PCAP_DIGITAL_AUDIO_INTERFACE_NETWORK = 0x00002000,
-+ PCAP_DIGITAL_AUDIO_INTERFACE_I2S = 0x00004000
-+}DIG_AUD_MODE_TYPE;
-+
-+typedef enum pcapMono
-+{
-+ PCAP_MONO_PGA_R_L_STEREO = 0x00000000,
-+ PCAP_MONO_PGA_RL = 0x00080000,
-+ PCAP_MONO_PGA_RL_3DB = 0x00100000,
-+ PCAP_MONO_PGA_RL_6DB = 0x00180000
-+}MONO_TYPE;
-+
-+typedef enum pcapVibratorVoltageLevel
-+{
-+ PCAP_VIBRATOR_VOLTAGE_LEVEL0 = 0x00000000,
-+ PCAP_VIBRATOR_VOLTAGE_LEVEL1 = 0x00100000,
-+ PCAP_VIBRATOR_VOLTAGE_LEVEL2 = 0x00200000,
-+ PCAP_VIBRATOR_VOLTAGE_LEVEL3 = 0x00300000
-+}VibratorVoltageLevel_TYPE;
-+
-+typedef enum pcapTouchScreenMode
-+{
-+ PCAP_TS_POSITION_X_MEASUREMENT = 0x00000000,
-+ PCAP_TS_POSITION_XY_MEASUREMENT = 0x00020000,
-+ PCAP_TS_PRESSURE_MEASUREMENT = 0x00040000,
-+ PCAP_TS_PLATE_X_MEASUREMENT = 0x00060000,
-+ PCAP_TS_PLATE_Y_MEASUREMENT = 0x00080000,
-+ PCAP_TS_STANDBY_MODE = 0x000a0000,
-+ PCAP_TS_NONTS_MODE = 0x000c0000
-+}TOUCH_SCREEN_DETECT_TYPE;
-+
-+typedef enum pcapADJRegister
-+{
-+ SSP_PCAP_ADJ_ISR_REGISTER = 0x00,
-+ SSP_PCAP_ADJ_MSR_REGISTER = 0x01,
-+ SSP_PCAP_ADJ_PSTAT_REGISTER = 0x02,
-+ SSP_PCAP_ADJ_VREG2_REGISTER = 0x06,
-+ SSP_PCAP_ADJ_AUX_VREG_REGISTER = 0x07,
-+ SSP_PCAP_ADJ_BATT_DAC_REGISTER = 0x08,
-+ SSP_PCAP_ADJ_ADC1_REGISTER = 0x09,
-+ SSP_PCAP_ADJ_ADC2_REGISTER = 0x0a,
-+ SSP_PCAP_ADJ_AUD_CODEC_REGISTER = 0x0b,
-+ SSP_PCAP_ADJ_AUD_RX_AMPS_REGISTER = 0x0c,
-+ SSP_PCAP_ADJ_ST_DAC_REGISTER = 0x0d,
-+ SSP_PCAP_ADJ_BUSCTRL_REGISTER = 0x14,
-+ SSP_PCAP_ADJ_PERIPH_REGISTER = 0x15,
-+ SSP_PCAP_ADJ_LOWPWR_CTRL_REGISTER = 0x18,
-+ SSP_PCAP_ADJ_TX_AUD_AMPS_REGISTER = 0x1a,
-+ SSP_PCAP_ADJ_GP_REG_REGISTER = 0x1b
-+}SSP_PCAP_SECONDARY_PROCESSOR_REGISTER;
-+
-+typedef enum pcapADJBit_SetType
-+{
-+ SSP_PCAP_ADJ_BIT_ISR_ADCDONEI = 0x00000001,
-+ SSP_PCAP_ADJ_BIT_ISR_TSI = 0x00000002,
-+ SSP_PCAP_ADJ_BIT_ISR_1HZI = 0x00000004,
-+ SSP_PCAP_ADJ_BIT_ISR_WHI = 0x00000008,
-+ SSP_PCAP_ADJ_BIT_ISR_WLI = 0x00000010,
-+ SSP_PCAP_ADJ_BIT_ISR_TODAI = 0x00000020,
-+ SSP_PCAP_ADJ_BIT_ISR_USB4VI = 0x00000040,
-+ SSP_PCAP_ADJ_BIT_ISR_ONOFFI = 0x00000080,
-+ SSP_PCAP_ADJ_BIT_ISR_ONOFF2I = 0x00000100,
-+ SSP_PCAP_ADJ_BIT_ISR_USB1VI = 0x00000200,
-+ SSP_PCAP_ADJ_BIT_ISR_MOBPORTI = 0x00000400,
-+ SSP_PCAP_ADJ_BIT_ISR_MB2I = 0x00000800,
-+ SSP_PCAP_ADJ_BIT_ISR_A1I = 0x00001000,
-+ SSP_PCAP_ADJ_BIT_ISR_STI = 0x00002000,
-+ SSP_PCAP_ADJ_BIT_ISR_PCI = 0x00004000,
-+ SSP_PCAP_ADJ_BIT_ISR_WARMI = 0x00008000,
-+ SSP_PCAP_ADJ_BIT_ISR_EOLI = 0x00010000,
-+ SSP_PCAP_ADJ_BIT_ISR_CLKI = 0x00020000,
-+ SSP_PCAP_ADJ_BIT_ISR_SYS_RSTI = 0x00040000,
-+ SSP_PCAP_ADJ_BIT_ISR_ADCDONE2I = 0x00100000,
-+ SSP_PCAP_ADJ_BIT_ISR_SOFT_RESETI = 0x00200000,
-+ SSP_PCAP_ADJ_BIT_ISR_MNEXBI = 0x00400000,
-+
-+ SSP_PCAP_ADJ_BIT_MSR_ADCDONEM = 0x04000001,
-+ SSP_PCAP_ADJ_BIT_MSR_TSM = 0x04000002,
-+ SSP_PCAP_ADJ_BIT_MSR_1HZM = 0x04000004,
-+ SSP_PCAP_ADJ_BIT_MSR_WHM = 0x04000008,
-+ SSP_PCAP_ADJ_BIT_MSR_WLM = 0x04000010,
-+ SSP_PCAP_ADJ_BIT_MSR_TODAM = 0x04000020,
-+ SSP_PCAP_ADJ_BIT_MSR_USB4VM = 0x04000040,
-+ SSP_PCAP_ADJ_BIT_MSR_ONOFFM = 0x04000080,
-+ SSP_PCAP_ADJ_BIT_MSR_ONOFF2M = 0x04000100,
-+ SSP_PCAP_ADJ_BIT_MSR_USB1VM = 0x04000200,
-+ SSP_PCAP_ADJ_BIT_MSR_MOBPORTM = 0x04000400,
-+ SSP_PCAP_ADJ_BIT_MSR_MB2M = 0x04000800,
-+ SSP_PCAP_ADJ_BIT_MSR_A1M = 0x04001000,
-+ SSP_PCAP_ADJ_BIT_MSR_STM = 0x04002000,
-+ SSP_PCAP_ADJ_BIT_MSR_PCM = 0x04004000,
-+ SSP_PCAP_ADJ_BIT_MSR_WARMM = 0x04008000,
-+ SSP_PCAP_ADJ_BIT_MSR_EOLM = 0x04010000,
-+ SSP_PCAP_ADJ_BIT_MSR_CLKM = 0x04020000,
-+ SSP_PCAP_ADJ_BIT_MSR_SYS_RSTM = 0x04040000,
-+ SSP_PCAP_ADJ_BIT_MSR_ADCDONE2M = 0x04100000,
-+ SSP_PCAP_ADJ_BIT_MSR_SOFT_RESETM = 0x04200000,
-+ SSP_PCAP_ADJ_BIT_MSR_MNEXBM = 0x04400000,
-+
-+ SSP_PCAP_ADJ_BIT_PSTAT_USBDET_4V = 0x08000040,
-+ SSP_PCAP_ADJ_BIT_PSTAT_ONOFFSNS = 0x08000080,
-+ SSP_PCAP_ADJ_BIT_PSTAT_ONOFFSNS2 = 0x08000100,
-+ SSP_PCAP_ADJ_BIT_PSTAT_USBDET_1V = 0x08000200,
-+ SSP_PCAP_ADJ_BIT_PSTAT_MOBSENSB = 0x08000400,
-+ SSP_PCAP_ADJ_BIT_PSTAT_MB2SNS = 0x08000800,
-+ SSP_PCAP_ADJ_BIT_PSTAT_A1SNS = 0x08001000,
-+ SSP_PCAP_ADJ_BIT_PSTAT_MSTB = 0x08002000,
-+ SSP_PCAP_ADJ_BIT_PSTAT_EOL_STAT = 0x08010000,
-+ SSP_PCAP_ADJ_BIT_PSTAT_CLK_STAT = 0x08020000,
-+ SSP_PCAP_ADJ_BIT_PSTAT_SYS_RST = 0x08040000,
-+ SSP_PCAP_ADJ_BIT_PSTAT_BATTFBSNS = 0x08080000,
-+ SSP_PCAP_ADJ_BIT_PSTAT_BATT_DET_IN_SNS = 0x08200000,
-+ SSP_PCAP_ADJ_BIT_PSTAT_MNEXBSNS = 0x08400000,
-+ SSP_PCAP_ADJ_BIT_PSTAT_WARM_SYS_RST = 0x08800000,
-+
-+ SSP_PCAP_ADJ_BIT_VREG2_V1_STBY = 0x18000001,
-+ SSP_PCAP_ADJ_BIT_VREG2_V2_STBY = 0x18000002,
-+ SSP_PCAP_ADJ_BIT_VREG2_V3_STBY = 0x18000004,
-+ SSP_PCAP_ADJ_BIT_VREG2_V4_STBY = 0x18000008,
-+ SSP_PCAP_ADJ_BIT_VREG2_V5_STBY = 0x18000010,
-+ SSP_PCAP_ADJ_BIT_VREG2_V6_STBY = 0x18000020,
-+ SSP_PCAP_ADJ_BIT_VREG2_V7_STBY = 0x18000040,
-+ SSP_PCAP_ADJ_BIT_VREG2_V8_STBY = 0x18000080,
-+ SSP_PCAP_ADJ_BIT_VREG2_V9_STBY = 0x18000100,
-+ SSP_PCAP_ADJ_BIT_VREG2_V10_STBY = 0x18000200,
-+ SSP_PCAP_ADJ_BIT_VREG2_V1_LOWPWR = 0x18000400,
-+ SSP_PCAP_ADJ_BIT_VREG2_V2_LOWPWR = 0x18000800,
-+ SSP_PCAP_ADJ_BIT_VREG2_V3_LOWPWR = 0x18001000,
-+ SSP_PCAP_ADJ_BIT_VREG2_V4_LOWPWR = 0x18002000,
-+ SSP_PCAP_ADJ_BIT_VREG2_V5_LOWPWR = 0x18004000,
-+ SSP_PCAP_ADJ_BIT_VREG2_V6_LOWPWR = 0x18008000,
-+ SSP_PCAP_ADJ_BIT_VREG2_V7_LOWPWR = 0x18010000,
-+ SSP_PCAP_ADJ_BIT_VREG2_V8_LOWPWR = 0x18020000,
-+ SSP_PCAP_ADJ_BIT_VREG2_V9_LOWPWR = 0x18040000,
-+ SSP_PCAP_ADJ_BIT_VREG2_V10_LOWPWR = 0x18080000,
-+
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_EN = 0x1c000002,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_0 = 0x1c000004,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_1 = 0x1c000008,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN = 0x1c000010,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_0 = 0x1c000020,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_1 = 0x1c000040,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_EN = 0x1c000080,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_0 = 0x1c000100,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_1 = 0x1c000200,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_2 = 0x1c000400,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_3 = 0x1c000800,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX4_EN = 0x1c001000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX4_0 = 0x1c002000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX4_1 = 0x1c004000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VSIM2_EN = 0x1c010000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VSIM_EN = 0x1c020000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VSIM_0 = 0x1c040000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN = 0x1c080000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_0 = 0x1c100000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_1 = 0x1c200000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_STBY = 0x1c400000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_LOWPWR = 0x1c800000,
-+ SSP_PCAP_ADJ_BIT_AUX_VREG_SW3_STBY = 0x1d000000,
-+
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_DAC0 = 0x20000001,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_DAC1 = 0x20000002,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_DAC2 = 0x20000004,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_DAC3 = 0x20000008,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_DAC4 = 0x20000010,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_DAC5 = 0x20000020,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_DAC6 = 0x20000040,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_DAC7 = 0x20000080,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_B_FDBK = 0x20000100,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_EXT_ISENSE = 0x20000200,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN0 = 0x20000400,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN1 = 0x20000800,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN2 = 0x20001000,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN3 = 0x20002000,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_I_COIN = 0x20004000,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_COIN_CH_EN = 0x20008000,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_SEL0 = 0x20020000,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_SEL1 = 0x20040000,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_SEL2 = 0x20080000,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_CMP_EN = 0x20100000,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_BATT_DET_EN = 0x20200000,
-+ SSP_PCAP_ADJ_BIT_BATT_DAC_THERMBIAS_CTRL = 0x20400000,
-+
-+ SSP_PCAP_ADJ_BIT_ADC1_ADEN = 0x24000001,
-+ SSP_PCAP_ADJ_BIT_ADC1_RAND = 0x24000002,
-+ SSP_PCAP_ADJ_BIT_ADC1_AD_SEL1 = 0x24000004,
-+ SSP_PCAP_ADJ_BIT_ADC1_AD_SEL2 = 0x24000008,
-+ SSP_PCAP_ADJ_BIT_ADC1_ADA10 = 0x24000010,
-+ SSP_PCAP_ADJ_BIT_ADC1_ADA11 = 0x24000020,
-+ SSP_PCAP_ADJ_BIT_ADC1_ADA12 = 0x24000040,
-+ SSP_PCAP_ADJ_BIT_ADC1_ADA20 = 0x24000080,
-+ SSP_PCAP_ADJ_BIT_ADC1_ADA21 = 0x24000100,
-+ SSP_PCAP_ADJ_BIT_ADC1_ADA22 = 0x24000200,
-+ SSP_PCAP_ADJ_BIT_ADC1_ATO0 = 0x24000400,
-+ SSP_PCAP_ADJ_BIT_ADC1_ATO1 = 0x24000800,
-+ SSP_PCAP_ADJ_BIT_ADC1_ATO2 = 0x24001000,
-+ SSP_PCAP_ADJ_BIT_ADC1_ATO3 = 0x24002000,
-+ SSP_PCAP_ADJ_BIT_ADC1_ATOX = 0x24004000,
-+ SSP_PCAP_ADJ_BIT_ADC1_MTR1 = 0x24008000,
-+ SSP_PCAP_ADJ_BIT_ADC1_MTR2 = 0x24010000,
-+ SSP_PCAP_ADJ_BIT_ADC1_TS_M0 = 0x24020000,
-+ SSP_PCAP_ADJ_BIT_ADC1_TS_M1 = 0x24040000,
-+ SSP_PCAP_ADJ_BIT_ADC1_TS_M2 = 0x24080000,
-+ SSP_PCAP_ADJ_BIT_ADC1_TS_REF_LOWPWR = 0x24100000,
-+ SSP_PCAP_ADJ_BIT_ADC1_TS_REFENB = 0x24200000,
-+ SSP_PCAP_ADJ_BIT_ADC1_BATT_I_POLARITY = 0x24400000,
-+ SSP_PCAP_ADJ_BIT_ADC1_BATT_I_ADC = 0x24800000,
-+
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD10 = 0x28000001,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD11 = 0x28000002,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD12 = 0x28000004,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD13 = 0x28000008,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD14 = 0x28000010,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD15 = 0x28000020,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD16 = 0x28000040,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD17 = 0x28000080,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD18 = 0x28000100,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD19 = 0x28000200,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD20 = 0x28000400,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD21 = 0x28000800,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD22 = 0x28001000,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD23 = 0x28002000,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD24 = 0x28004000,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD25 = 0x28008000,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD26 = 0x28010000,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD27 = 0x28020000,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD28 = 0x28040000,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADD29 = 0x28080000,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADINC1 = 0x28100000,
-+ SSP_PCAP_ADJ_BIT_ADC2_ADINC2 = 0x28200000,
-+ SSP_PCAP_ADJ_BIT_ADC2_ASC = 0x28400000,
-+
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_AUDIHPF = 0x2c000001,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_SMB = 0x2c000002,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_AUDOHPF = 0x2c000004,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_CD_TS = 0x2c000008,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_DLM = 0x2c000010,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_ADITH = 0x2c000020,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK0 = 0x2c000040,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK1 = 0x2c000080,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK2 = 0x2c000100,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_CLK_INV = 0x2c000200,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_FS_INV = 0x2c000400,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_DF_RESET = 0x2c000800,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_EN = 0x2c001000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK_EN = 0x2c002000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_FS_8K_16K = 0x2c004000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_DIG_AUD_IN = 0x2c008000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_CLK_IN_SEL = 0x2c010000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2_MUX = 0x2c020000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG0 = 0x2c040000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG1 = 0x2c080000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG2 = 0x2c100000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG3 = 0x2c200000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG4 = 0x2c400000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG_PRI_ADJ = 0x2c800000,
-+ SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_PRI_ADJ = 0x2c200000,
-+
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1_EN = 0x30000001,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A2_EN = 0x30000002,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A4_EN = 0x30000010,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_ARIGHT_EN = 0x30000020,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_ALEFT_EN = 0x30000040,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_CD_BYP = 0x30000080,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_CDC_SW = 0x30000100,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_ST_DAC_SW = 0x30000200,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_IN_SW = 0x30000400,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_R_EN = 0x30000800,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_L_EN = 0x30001000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG0 = 0x30002000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG1 = 0x30004000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG2 = 0x30008000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG3 = 0x30010000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1CTRL = 0x30020000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_MONO0 = 0x30080000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_MONO1 = 0x30100000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG_PRI_ADJ = 0x30200000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_MONO_PRI_ADJ = 0x30400000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_RX_PRI_ADJ0 = 0x30800000,
-+ SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_RX_PRI_ADJ1 = 0x31000000,
-+
-+ SSP_PCAP_ADJ_BIT_ST_DAC_SMB_ST_DAC = 0x34000001,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_STDET_EN = 0x34000002,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK0 = 0x34000004,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK1 = 0x34000008,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK2 = 0x34000010,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK_EN = 0x34000020,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_DF_RESET_ST_DAC = 0x34000040,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_EN = 0x34000080,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_SR0 = 0x34000100,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_SR1 = 0x34000200,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_SR2 = 0x34000400,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_SR3 = 0x34000800,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_DIG_AUD_IN_ST_DAC = 0x34001000,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_DIG_AUD_FS0 = 0x34002000,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_DIG_AUD_FS1 = 0x34004000,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_BCLK0 = 0x34008000,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_BCLK1 = 0x34010000,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK_INV = 0x34020000,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_ST_FS_INV = 0x34040000,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_CLK_IN_SEL = 0x34080000,
-+ SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_PRI_ADJ = 0x35000000,
-+
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_FSENB = 0x50000001,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_USB_SUSPEND = 0x50000002,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PU = 0x50000004,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PD = 0x50000008,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_VUSB_EN = 0x50000010,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PS = 0x50000020,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_VUSB_MSTR_EN = 0x50000040,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_VBUS_PD_ENB = 0x50000080,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_CURRLIM = 0x50000100,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_RS232ENB = 0x50000200,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_RS232_DIR = 0x50000400,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_SE0_CONN = 0x50000800,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PDM = 0x50001000,
-+ SSP_PCAP_ADJ_BIT_BUSCTRL_BUS_PRI_ADJ = 0x51000000,
-+
-+ SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL0 = 0x54000001,
-+ SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL1 = 0x54000002,
-+ SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL2 = 0x54000004,
-+ SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL3 = 0x54000008,
-+ SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL4 = 0x54000010,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDR_EN = 0x54000020,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDG_EN = 0x54000040,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL0 = 0x54000080,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL1 = 0x54000100,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL2 = 0x54000200,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL3 = 0x54000400,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL0 = 0x54000800,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL1 = 0x54001000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL2 = 0x54002000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL3 = 0x54004000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDR_I0 = 0x54008000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDR_I1 = 0x54010000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDG_I0 = 0x54020000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_LEDG_I1 = 0x54040000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_SKIP = 0x54080000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL0 = 0x54100000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL1 = 0x54200000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL2 = 0x54400000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL3 = 0x54800000,
-+ SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL4 = 0x55000000,
-+
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_STBY = 0x60000001,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_LOWPWR = 0x60000002,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX3_STBY = 0x60000004,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX3_LOWPWR = 0x60000008,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX4_STBY = 0x60000010,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX4_LOWPWR = 0x60000020,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VSIM_LOWPWR = 0x60000040,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VSIM2_LOWPWR = 0x60000080,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE00 = 0x60000100,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE01 = 0x60000200,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE10 = 0x60000400,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE11 = 0x60000800,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW10_DVS = 0x60001000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW11_DVS = 0x60002000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW12_DVS = 0x60004000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW13_DVS = 0x60008000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE00 = 0x60010000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE01 = 0x60020000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE10 = 0x60040000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE11 = 0x60080000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW20_DVS = 0x60100000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW21_DVS = 0x60200000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW22_DVS = 0x60400000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW23_DVS = 0x60800000,
-+ SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VC_STBY = 0x61000000,
-+
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG0 = 0x68000001,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG1 = 0x68000002,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG2 = 0x68000004,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG3 = 0x68000008,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG4 = 0x68000010,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A3_EN = 0x68000020,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A3_MUX = 0x68000040,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A5_EN = 0x68000080,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A5_MUX = 0x68000100,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_EXT_MIC_MUX = 0x68000200,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_MB_ON2 = 0x68000400,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_MB_ON1 = 0x68000800,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A1ID_TX = 0x68001000,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A1_CONFIG = 0x68002000,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AHS_CONFIG = 0x68004000,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A2_CONFIG = 0x68008000,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIO_LOWPWR = 0x68080000,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIO_STBY = 0x68100000,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_V2_EN_2 = 0x68200000,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG_PRI_ADJ = 0x68400000,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_TX_PRI_ADJ0 = 0x68800000,
-+ SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_TX_PRI_ADJ1 = 0x69000000,
-+
-+ SSP_PCAP_ADJ_BIT_SYS_RST_CLR = 0x6c000001,
-+ SSP_PCAP_ADJ_BIT_SYS_RST_MODE0 = 0x6c000002,
-+ SSP_PCAP_ADJ_BIT_SYS_RST_MODE1 = 0x6c000004,
-+ SSP_PCAP_ADJ_BIT_SYS_VFLASH_0 = 0x6c000008,
-+ SSP_PCAP_ADJ_BIT_SYS_VFLASH_1 = 0x6c000010,
-+ SSP_PCAP_ADJ_BIT_SYS_MID_SELECT = 0x6c000020,
-+ SSP_PCAP_ADJ_BIT_SYS_MID_FET = 0x6c000040,
-+ SSP_PCAP_ADJ_BIT_SYS_MAIN_LOW = 0x6c000080,
-+ SSP_PCAP_ADJ_BIT_SYS_BATTFB_DIS = 0x6c000100,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG9 = 0x6c000200,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG10 = 0x6c000400,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG11 = 0x6c000800,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG12 = 0x6c001000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG13 = 0x6c002000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG14 = 0x6c004000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG15 = 0x6c008000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG16 = 0x6c010000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG17 = 0x6c020000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG18 = 0x6c040000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG19 = 0x6c080000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG20 = 0x6c100000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG21 = 0x6c200000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG22 = 0x6c400000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG23 = 0x6c800000,
-+ SSP_PCAP_ADJ_BIT_SYS_GP_REG24 = 0x6d000000
-+
-+}SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE;
-+
-+/************************ FUNCTION PROTOTYPES **************************************/
-+extern void ssp_pcap_init(void);
-+extern void ssp_pcap_release(void);
-+
-+extern void ssp_pcap_open(SSP_PCAP_INIT_DRIVER_TYPE portType);
-+extern void ssp_pcap_close(void);
-+
-+extern void ssp_pcap_intoSleep_callBack(void);
-+extern void ssp_pcap_wakeUp_callBack(void);
-+
-+
-+extern SSP_PCAP_STATUS SSP_PCAP_write_data_to_PCAP(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER ssp_pcap_register,U32 ssp_pcap_register_value);
-+extern SSP_PCAP_STATUS SSP_PCAP_read_data_from_PCAP(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER ssp_pcap_register,P_U32 p_ssp_pcap_register_value);
-+
-+extern SSP_PCAP_STATUS SSP_PCAP_bit_set(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
-+extern SSP_PCAP_STATUS SSP_PCAP_bit_clean(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
-+extern SSP_PCAP_BIT_STATUS SSP_PCAP_get_bit_from_buffer(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
-+extern SSP_PCAP_BIT_STATUS SSP_PCAP_get_bit_from_PCAP(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
-+extern U32 SSP_PCAP_get_register_value_from_buffer(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER ssp_pcap_register ) ;
-+
-+extern SSP_PCAP_STATUS SSP_PCAP_TSI_mode_set(TOUCH_SCREEN_DETECT_TYPE mode_Type );
-+extern SSP_PCAP_STATUS SSP_PCAP_TSI_start_XY_read(void);
-+extern SSP_PCAP_STATUS SSP_PCAP_TSI_get_XY_value(P_U16 p_x,P_U16 p_y);
-+extern SSP_PCAP_STATUS SSP_PCAP_CDC_CLK_set(PHONE_CDC_CLOCK_TYPE clkType);
-+
-+extern SSP_PCAP_STATUS SSP_PCAP_CDC_SR_set(ST_SAMPLE_RATE_TYPE srType);
-+extern SSP_PCAP_STATUS SSP_PCAP_BCLK_set(ST_BCLK_TIME_SLOT_TYPE bclkType);
-+extern SSP_PCAP_STATUS SSP_PCAP_STCLK_set(ST_CLK_TYPE stClkType);
-+extern SSP_PCAP_STATUS SSP_PCAP_DIG_AUD_FS_set(DIG_AUD_MODE_TYPE fsType);
-+extern SSP_PCAP_STATUS SSP_PCAP_AUDIG_set(U32 audioInGain);
-+extern SSP_PCAP_STATUS SSP_PCAP_MONO_set(MONO_TYPE monoType);
-+extern SSP_PCAP_STATUS SSP_PCAP_AUDOG_set(U32 audioOutGain);
-+
-+extern SSP_PCAP_STATUS SSP_PCAP_V_VIB_level_set(VibratorVoltageLevel_TYPE VIBLevelType);
-+extern SSP_PCAP_STATUS SSP_PCAP_configure_USB_UART_transeiver(SSP_PCAP_PORT_TYPE portType);
-+extern SSP_PCAP_BIT_STATUS SSP_PCAP_get_audio_in_status(void);
-+
-+/* for log */
-+extern void pcap_log_add_pure_data(u8* pData,u32 len);
-+extern void pcap_log_add_data(u8* pData,u32 len);
-+
-+/* screen lock on/off handler */
-+extern void ssp_pcap_screenlock_lock(u32 data);
-+extern void ssp_pcap_screenlock_unlock(u32 data);
-+
++/* driver configuration */
++#define PCAP_CS_AH (1 << 0) /* CS pin is active high */
++#define PCAP_MCI_SD (1 << 1) /* SD card slot */
++#define PCAP_MCI_TF (1 << 2) /* TF card slot */
++
++#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
++#define PCAP_REGISTER_READ_OP_BIT 0x00000000
++
++#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
++#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
++#define PCAP_REGISTER_ADDRESS_SHIFT 26
++#define PCAP_REGISTER_NUMBER 32
++#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
++#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
++
++
++#define pbit(reg, bit) ((reg << PCAP_REGISTER_ADDRESS_SHIFT) | bit)
++
++/* registers acessible by both pcap ports */
++#define PCAP_REG_ISR 0x0 /* Interrupt Status */
++#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
++#define PCAP_REG_PSTAT 0x2 /* Processor Status */
++#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
++#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
++#define PCAP_REG_BATT 0x8 /* Battery Control */
++#define PCAP_REG_ADC1 0x9 /* AD Control */
++#define PCAP_REG_ADC2 0xa /* AD Result */
++#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
++#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
++#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
++#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
++#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
++#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
++#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
++#define PCAP_REG_GP 0x1b /* General Purpose */
++
++/* registers acessible by pcap port 1 only (a1200, e2 & e6) */
++#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
++#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
++#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
++#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
++#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
++#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
++#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
++#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
++#define PCAP_REG_PWR 0x13 /* Power Control */
++#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
++#define PCAP_REG_VENDOR_REV 0x17
++#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
++
++/* interrupts - registers 0, 1, 2, 3 */
++#define PCAP_IRQ_ADCDONE (1 << 0) /* AD Conversion Done Port 1 */
++#define PCAP_IRQ_TS (1 << 1) /* Touch Screen */
++#define PCAP_IRQ_1HZ (1 << 2) /* 1HZ Timer */
++#define PCAP_IRQ_WH (1 << 3)
++#define PCAP_IRQ_WL (1 << 4)
++#define PCAP_IRQ_TODA (1 << 5)
++#define PCAP_IRQ_USB4V (1 << 6)
++#define PCAP_IRQ_ONOFF (1 << 7)
++#define PCAP_IRQ_ONOFF2 (1 << 8)
++#define PCAP_IRQ_USB1V (1 << 9)
++#define PCAP_IRQ_MOBPORT (1 << 10)
++#define PCAP_IRQ_MB2 (1 << 11) /* Mic */
++#define PCAP_IRQ_A1 (1 << 12) /* Audio jack */
++#define PCAP_IRQ_ST (1 << 13)
++#define PCAP_IRQ_PC (1 << 14)
++#define PCAP_IRQ_WARM (1 << 15)
++#define PCAP_IRQ_EOL (1 << 16)
++#define PCAP_IRQ_CLK (1 << 17)
++#define PCAP_IRQ_SYSRST (1 << 18)
++#define PCAP_IRQ_ADCDONE2 (1 << 20) /* AD Conversion Done Port 2 */
++#define PCAP_IRQ_SOFTRESET (1 << 21)
++#define PCAP_IRQ_MNEXB (1 << 22)
++
++#define PCAP_BIT_VREG2_V1_STBY pbit(PCAP_REG_VREG2, (1 << 0))
++#define PCAP_BIT_VREG2_V2_STBY pbit(PCAP_REG_VREG2, (1 << 1))
++#define PCAP_BIT_VREG2_V3_STBY pbit(PCAP_REG_VREG2, (1 << 2))
++#define PCAP_BIT_VREG2_V4_STBY pbit(PCAP_REG_VREG2, (1 << 3))
++#define PCAP_BIT_VREG2_V5_STBY pbit(PCAP_REG_VREG2, (1 << 4))
++#define PCAP_BIT_VREG2_V6_STBY pbit(PCAP_REG_VREG2, (1 << 5))
++#define PCAP_BIT_VREG2_V7_STBY pbit(PCAP_REG_VREG2, (1 << 6))
++#define PCAP_BIT_VREG2_V8_STBY pbit(PCAP_REG_VREG2, (1 << 7))
++#define PCAP_BIT_VREG2_V9_STBY pbit(PCAP_REG_VREG2, (1 << 8))
++#define PCAP_BIT_VREG2_V10_STBY pbit(PCAP_REG_VREG2, (1 << 9))
++#define PCAP_BIT_VREG2_V1_LOWPWR pbit(PCAP_REG_VREG2, (1 << 10))
++#define PCAP_BIT_VREG2_V2_LOWPWR pbit(PCAP_REG_VREG2, (1 << 11))
++#define PCAP_BIT_VREG2_V3_LOWPWR pbit(PCAP_REG_VREG2, (1 << 12))
++#define PCAP_BIT_VREG2_V4_LOWPWR pbit(PCAP_REG_VREG2, (1 << 13))
++#define PCAP_BIT_VREG2_V5_LOWPWR pbit(PCAP_REG_VREG2, (1 << 14))
++#define PCAP_BIT_VREG2_V6_LOWPWR pbit(PCAP_REG_VREG2, (1 << 15))
++#define PCAP_BIT_VREG2_V7_LOWPWR pbit(PCAP_REG_VREG2, (1 << 16))
++#define PCAP_BIT_VREG2_V8_LOWPWR pbit(PCAP_REG_VREG2, (1 << 17))
++#define PCAP_BIT_VREG2_V9_LOWPWR pbit(PCAP_REG_VREG2, (1 << 18))
++#define PCAP_BIT_VREG2_V10_LOWPWR pbit(PCAP_REG_VREG2, (1 << 19))
++
++#define PCAP_BIT_AUXVREG_VAUX1_EN pbit(PCAP_REG_AUXVREG, (1 << 1))
++#define PCAP_AUXVREG_VAUX1_MASK 0x0000000c
++#define PCAP_AUXVREG_VAUX1_SHIFT 2
++#define PCAP_BIT_AUXVREG_VAUX2_EN pbit(PCAP_REG_AUXVREG, (1 << 4))
++#define PCAP_AUXVREG_VAUX2_MASK 0x00000060
++#define PCAP_AUXVREG_VAUX2_SHIFT 5
++#define PCAP_BIT_AUXVREG_VAUX3_EN pbit(PCAP_REG_AUXVREG, (1 << 7))
++#define PCAP_AUXVREG_VAUX3_MASK 0x00000f00
++#define PCAP_AUXVREG_VAUX3_SHIFT 8
++#define PCAP_BIT_AUXVREG_VAUX4_EN pbit(PCAP_REG_AUXVREG, (1 << 12))
++#define PCAP_AUXVREG_VAUX4_MASK 0x00006000
++#define PCAP_AUXVREG_VAUX4_SHIFT 13
++#define PCAP_BIT_AUXVREG_VSIM2_EN pbit(PCAP_REG_AUXVREG, (1 << 16))
++#define PCAP_BIT_AUXVREG_VSIM_EN pbit(PCAP_REG_AUXVREG, (1 << 17))
++#define PCAP_BIT_AUXVREG_VSIM_0 pbit(PCAP_REG_AUXVREG, (1 << 18))
++#define PCAP_BIT_AUXVREG_V_VIB_EN pbit(PCAP_REG_AUXVREG, (1 << 19))
++#define PCAP_AUXVREG_V_VIB_MASK 0x00300000
++#define PCAP_AUXVREG_V_VIB_SHIFT 20
++#define PCAP_BIT_AUXVREG_VAUX1_STBY pbit(PCAP_REG_AUXVREG, (1 << 22))
++#define PCAP_BIT_AUXVREG_VAUX1_LOWPWR pbit(PCAP_REG_AUXVREG, (1 << 23))
++#define PCAP_BIT_AUXVREG_SW3_STBY pbit(PCAP_REG_AUXVREG, (1 << 24))
++
++#define PCAP_BATT_DAC_MASK 0x000000ff
++#define PCAP_BATT_DAC_SHIFT 0
++#define PCAP_BIT_BATT_B_FDBK pbit(PCAP_REG_BATT, (1 << 8))
++#define PCAP_BIT_BATT_EXT_ISENSE pbit(PCAP_REG_BATT, (1 << 9))
++#define PCAP_BATT_V_COIN_MASK 0x00003c00
++#define PCAP_BATT_V_COIN_SHIFT 10
++#define PCAP_BIT_BATT_I_COIN pbit(PCAP_REG_BATT, (1 << 14))
++#define PCAP_BIT_BATT_COIN_CH_EN pbit(PCAP_REG_BATT, (1 << 15))
++#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
++#define PCAP_BATT_EOL_SEL_SHIFT 17
++#define PCAP_BIT_BATT_EOL_CMP_EN pbit(PCAP_REG_BATT, (1 << 20))
++#define PCAP_BIT_BATT_BATT_DET_EN pbit(PCAP_REG_BATT, (1 << 21))
++#define PCAP_BIT_BATT_THERMBIAS_CTRL pbit(PCAP_REG_BATT, (1 << 22))
++
++#define PCAP_BIT_ADC1_ADEN pbit(PCAP_REG_ADC1, (1 << 0))
++#define PCAP_BIT_ADC1_RAND pbit(PCAP_REG_ADC1, (1 << 1))
++#define PCAP_BIT_ADC1_AD_SEL1 pbit(PCAP_REG_ADC1, (1 << 2))
++#define PCAP_BIT_ADC1_AD_SEL2 pbit(PCAP_REG_ADC1, (1 << 3))
++#define PCAP_ADC1_ADA1_MASK 0x00000070
++#define PCAP_ADC1_ADA1_SHIFT 4
++#define PCAP_ADC1_ADA2_MASK 0x00000380
++#define PCAP_ADC1_ADA2_SHIFT 7
++#define PCAP_ADC1_ATO_MASK 0x00003c00
++#define PCAP_ADC1_ATO_SHIFT 10
++#define PCAP_BIT_ADC1_ATOX pbit(PCAP_REG_ADC1, (1 << 14))
++#define PCAP_BIT_ADC1_MTR1 pbit(PCAP_REG_ADC1, (1 << 15))
++#define PCAP_BIT_ADC1_MTR2 pbit(PCAP_REG_ADC1, (1 << 16))
++#define PCAP_ADC1_TS_M_MASK 0x000e0000
++#define PCAP_ADC1_TS_M_SHIFT 17
++#define PCAP_BIT_ADC1_TS_REF_LOWPWR pbit(PCAP_REG_ADC1, (1 << 20))
++#define PCAP_BIT_ADC1_TS_REFENB pbit(PCAP_REG_ADC1, (1 << 21))
++#define PCAP_BIT_ADC1_BATT_I_POLARITY pbit(PCAP_REG_ADC1, (1 << 22))
++#define PCAP_BIT_ADC1_BATT_I_ADC pbit(PCAP_REG_ADC1, (1 << 23))
++
++#define PCAP_ADC2_ADD1_MASK 0x000003ff
++#define PCAP_ADC2_ADD1_SHIFT 0
++#define PCAP_ADC2_ADD2_MASK 0x000ffc00
++#define PCAP_ADC2_ADD2_SHIFT 10
++#define PCAP_BIT_ADC2_ADINC1 pbit(PCAP_REG_ADC2, (1 << 20))
++#define PCAP_BIT_ADC2_ADINC2 pbit(PCAP_REG_ADC2, (1 << 21))
++#define PCAP_BIT_ADC2_ASC pbit(PCAP_REG_ADC2, (1 << 22))
++
++#define PCAP_BIT_BUSCTRL_FSENB 0x50000001
++#define PCAP_BIT_BUSCTRL_USB_SUSPEND 0x50000002
++#define PCAP_BIT_BUSCTRL_USB_PU 0x50000004
++#define PCAP_BIT_BUSCTRL_USB_PD 0x50000008
++#define PCAP_BIT_BUSCTRL_VUSB_EN 0x50000010
++#define PCAP_BIT_BUSCTRL_USB_PS 0x50000020
++#define PCAP_BIT_BUSCTRL_VUSB_MSTR_EN 0x50000040
++#define PCAP_BIT_BUSCTRL_VBUS_PD_ENB 0x50000080
++#define PCAP_BIT_BUSCTRL_CURRLIM 0x50000100
++#define PCAP_BIT_BUSCTRL_RS232ENB 0x50000200
++#define PCAP_BIT_BUSCTRL_RS232_DIR 0x50000400
++#define PCAP_BIT_BUSCTRL_SE0_CONN 0x50000800
++#define PCAP_BIT_BUSCTRL_USB_PDM 0x50001000
++#define PCAP_BIT_BUSCTRL_BUS_PRI_ADJ 0x51000000
++
++#define PCAP_BIT_PERIPH_BL_CTRL0 0x54000001
++#define PCAP_BIT_PERIPH_BL_CTRL1 0x54000002
++#define PCAP_BIT_PERIPH_BL_CTRL2 0x54000004
++#define PCAP_BIT_PERIPH_BL_CTRL3 0x54000008
++#define PCAP_BIT_PERIPH_BL_CTRL4 0x54000010
++#define PCAP_BIT_PERIPH_LEDR_EN 0x54000020
++#define PCAP_BIT_PERIPH_LEDG_EN 0x54000040
++#define PCAP_BIT_PERIPH_LEDR_CTRL0 0x54000080
++#define PCAP_BIT_PERIPH_LEDR_CTRL1 0x54000100
++#define PCAP_BIT_PERIPH_LEDR_CTRL2 0x54000200
++#define PCAP_BIT_PERIPH_LEDR_CTRL3 0x54000400
++#define PCAP_BIT_PERIPH_LEDG_CTRL0 0x54000800
++#define PCAP_BIT_PERIPH_LEDG_CTRL1 0x54001000
++#define PCAP_BIT_PERIPH_LEDG_CTRL2 0x54002000
++#define PCAP_BIT_PERIPH_LEDG_CTRL3 0x54004000
++#define PCAP_BIT_PERIPH_LEDR_I0 0x54008000
++#define PCAP_BIT_PERIPH_LEDR_I1 0x54010000
++#define PCAP_BIT_PERIPH_LEDG_I0 0x54020000
++#define PCAP_BIT_PERIPH_LEDG_I1 0x54040000
++#define PCAP_BIT_PERIPH_SKIP 0x54080000
++#define PCAP_BIT_PERIPH_BL2_CTRL0 0x54100000
++#define PCAP_BIT_PERIPH_BL2_CTRL1 0x54200000
++#define PCAP_BIT_PERIPH_BL2_CTRL2 0x54400000
++#define PCAP_BIT_PERIPH_BL2_CTRL3 0x54800000
++#define PCAP_BIT_PERIPH_BL2_CTRL4 0x55000000
++
++#define PCAP_BIT_LOWPWR_VAUX2_STBY 0x60000001
++#define PCAP_BIT_LOWPWR_VAUX2_LOWPWR 0x60000002
++#define PCAP_BIT_LOWPWR_VAUX3_STBY 0x60000004
++#define PCAP_BIT_LOWPWR_VAUX3_LOWPWR 0x60000008
++#define PCAP_BIT_LOWPWR_VAUX4_STBY 0x60000010
++#define PCAP_BIT_LOWPWR_VAUX4_LOWPWR 0x60000020
++#define PCAP_BIT_LOWPWR_VSIM_LOWPWR 0x60000040
++#define PCAP_BIT_LOWPWR_VSIM2_LOWPWR 0x60000080
++#define PCAP_BIT_LOWPWR_SW1_MODE00 0x60000100
++#define PCAP_BIT_LOWPWR_SW1_MODE01 0x60000200
++#define PCAP_BIT_LOWPWR_SW1_MODE10 0x60000400
++#define PCAP_BIT_LOWPWR_SW1_MODE11 0x60000800
++#define PCAP_BIT_LOWPWR_SW10_DVS 0x60001000
++#define PCAP_BIT_LOWPWR_SW11_DVS 0x60002000
++#define PCAP_BIT_LOWPWR_SW12_DVS 0x60004000
++#define PCAP_BIT_LOWPWR_SW13_DVS 0x60008000
++#define PCAP_BIT_LOWPWR_SW2_MODE00 0x60010000
++#define PCAP_BIT_LOWPWR_SW2_MODE01 0x60020000
++#define PCAP_BIT_LOWPWR_SW2_MODE10 0x60040000
++#define PCAP_BIT_LOWPWR_SW2_MODE11 0x60080000
++#define PCAP_BIT_LOWPWR_SW20_DVS 0x60100000
++#define PCAP_BIT_LOWPWR_SW21_DVS 0x60200000
++#define PCAP_BIT_LOWPWR_SW22_DVS 0x60400000
++#define PCAP_BIT_LOWPWR_SW23_DVS 0x60800000
++#define PCAP_BIT_LOWPWR_VC_STBY 0x61000000
++
++extern int ezx_pcap_write(u_int8_t, u_int32_t);
++extern int ezx_pcap_read(u_int8_t, u_int32_t *);
++extern int ezx_pcap_bit_set(u_int32_t, u_int8_t);
++extern int ezx_pcap_bit_get(u_int32_t);
++extern void ezx_pcap_vibrator_level(u_int32_t);
+#endif
Index: linux-2.6.21/include/asm-arm/arch-pxa/irqs.h
===================================================================
---- linux-2.6.21.orig/include/asm-arm/arch-pxa/irqs.h 2007-06-29 01:06:37.000000000 -0300
-+++ linux-2.6.21/include/asm-arm/arch-pxa/irqs.h 2007-06-29 01:07:18.000000000 -0300
+--- linux-2.6.21.orig/include/asm-arm/arch-pxa/irqs.h 2007-08-31 22:28:17.000000000 -0300
++++ linux-2.6.21/include/asm-arm/arch-pxa/irqs.h 2007-08-31 22:34:36.000000000 -0300
+@@ -85,7 +85,7 @@
+ * within sensible limits.
+ */
+ #define IRQ_BOARD_START (IRQ_GPIO(PXA_LAST_GPIO) + 1)
+-#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
++#define IRQ_BOARD_END (IRQ_BOARD_START + 22)
+
+ #define IRQ_SA1111_START (IRQ_BOARD_END)
+ #define IRQ_GPAIN0 (IRQ_BOARD_END + 0)
@@ -176,7 +176,8 @@
#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
#elif defined(CONFIG_ARCH_LUBBOCK) || \
#define NR_IRQS (IRQ_BOARD_END)
#else
#define NR_IRQS (IRQ_BOARD_START)
-@@ -222,3 +223,13 @@
+@@ -222,3 +223,28 @@
#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1)
#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
+#define EZX_IRQ_ADCDONE EZX_IRQ(4)
+#define EZX_IRQ_TS EZX_IRQ(5) /* TS touch */
+#define EZX_IRQ_ADCDONE2 EZX_IRQ(6) /* TS x/y ADC ready */
++#define EZX_IRQ_WH EZX_IRQ(7)
++#define EZX_IRQ_WL EZX_IRQ(8)
++#define EZX_IRQ_ONOFF EZX_IRQ(9)
++#define EZX_IRQ_ONOFF2 EZX_IRQ(10)
++#define EZX_IRQ_MOBPORT EZX_IRQ(11)
++#define EZX_IRQ_TODA EZX_IRQ(12)
++#define EZX_IRQ_1HZ EZX_IRQ(13)
++#define EZX_IRQ_MNEXB EZX_IRQ(14)
++#define EZX_IRQ_ST EZX_IRQ(15)
++#define EZX_IRQ_PC EZX_IRQ(16)
++#define EZX_IRQ_SYSRST EZX_IRQ(17)
++#define EZX_IRQ_SOFTRESET EZX_IRQ(18)
++#define EZX_IRQ_EOL EZX_IRQ(19)
++#define EZX_IRQ_CLK EZX_IRQ(20)
++#define EZX_IRQ_WARM EZX_IRQ(21)
Index: linux-2.6.21/arch/arm/mach-pxa/Kconfig
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/Kconfig 2007-06-29 01:07:18.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/Kconfig 2007-08-01 20:14:28.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/Kconfig 2007-08-31 22:33:05.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/Kconfig 2007-09-07 11:06:01.000000000 -0300
@@ -105,6 +105,9 @@
config EZX_BP
bool "BP Control code for EZX Platform"
endmenu
Index: linux-2.6.21/arch/arm/mach-pxa/Makefile
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/Makefile 2007-06-29 01:07:18.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/Makefile 2007-08-01 20:14:28.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/Makefile 2007-08-31 22:33:05.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/Makefile 2007-09-07 11:06:01.000000000 -0300
@@ -25,6 +25,7 @@
obj-$(CONFIG_PXA_EZX_A1200) += ezx-a1200.o
obj-$(CONFIG_PXA_EZX_E6) += ezx-e6.o
--- /dev/null
+Index: linux-2.6.21/drivers/i2c/i2c-core.c
+===================================================================
+--- linux-2.6.21.orig/drivers/i2c/i2c-core.c 2007-08-20 21:59:45.000000000 +0800
++++ linux-2.6.21/drivers/i2c/i2c-core.c 2007-08-20 22:03:12.000000000 +0800
+@@ -365,8 +365,10 @@
+ list_for_each(item,&adapters) {
+ adapter = list_entry(item, struct i2c_adapter, list);
+ driver->attach_adapter(adapter);
++ goto out; // Alex added for fix the bug otherwise system will be crashed. FIXME
+ }
+ }
++out:
+
+ mutex_unlock(&core_lists);
+ return 0;
Index: linux-2.6.21/drivers/input/touchscreen/Kconfig
===================================================================
---- linux-2.6.21.orig/drivers/input/touchscreen/Kconfig 2007-06-02 20:17:58.000000000 -0300
-+++ linux-2.6.21/drivers/input/touchscreen/Kconfig 2007-06-02 20:18:40.000000000 -0300
+--- linux-2.6.21.orig/drivers/input/touchscreen/Kconfig 2007-08-31 22:27:48.000000000 -0300
++++ linux-2.6.21/drivers/input/touchscreen/Kconfig 2007-08-31 23:06:39.000000000 -0300
@@ -164,4 +164,13 @@
To compile this driver as a module, choose M here: the
module will be called ucb1400_ts.
Index: linux-2.6.21/drivers/input/touchscreen/pcap_ts.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.21/drivers/input/touchscreen/pcap_ts.c 2007-06-02 20:19:39.000000000 -0300
-@@ -0,0 +1,372 @@
++++ linux-2.6.21/drivers/input/touchscreen/pcap_ts.c 2007-08-31 23:57:56.000000000 -0300
+@@ -0,0 +1,331 @@
+/*
+ * pcap_ts.c - Touchscreen driver for Motorola PCAP2 based touchscreen as found
+ * in the EZX phone platform.
+#define DEBUGP(x, args ...)
+#endif
+
-+#define PRESSURE 1
-+#define COORDINATE 2
-+#define STANDBY 3
-+
-+extern int ezx_pcap_read(u_int8_t, u_int32_t *);
-+extern int ezx_pcap_write(u_int8_t, u_int32_t);
-+extern int ezx_pcap_bit_set(u_int32_t, u_int8_t);
++#define POSITION_X_MEASUREMENT 0
++#define POSITION_XY_MEASUREMENT 1
++#define PRESSURE_MEASUREMENT 2
++#define PLATE_X_MEASUREMENT 3
++#define PLATE_Y_MEASUREMENT 4
++#define STANDBY_MODE 5
++#define NONTS_MODE 6
+
+struct pcap_ts {
+ int irq_xy;
+ int irq_touch;
+ struct input_dev *input;
+ struct timer_list timer;
-+
+ u_int16_t x, y;
+ u_int16_t pressure;
-+
+ u_int8_t read_state;
+};
+
+#define SAMPLE_INTERVAL (HZ/50)
+
+
-+static void pcap_ts_mode(u_int32_t mode)
++static void pcap_ts_mode(struct pcap_ts *pcap_ts, u_int32_t mode)
+{
+ u_int32_t tmp;
+
-+ ezx_pcap_read(SSP_PCAP_ADJ_ADC1_REGISTER, &tmp);
-+ tmp &= ~SSP_PCAP_TOUCH_PANEL_POSITION_DETECT_MODE_MASK;
-+ tmp |= mode;
-+ ezx_pcap_write(SSP_PCAP_ADJ_ADC1_REGISTER, tmp);
++ pcap_ts->read_state = mode;
++ ezx_pcap_read(PCAP_REG_ADC1, &tmp);
++ tmp &= ~PCAP_ADC1_TS_M_MASK;
++ tmp |= ((mode << PCAP_ADC1_TS_M_SHIFT) & PCAP_ADC1_TS_M_MASK);
++ ezx_pcap_write(PCAP_REG_ADC1, tmp);
+}
+
-+/* issue a XY read command to the ADC of PCAP2. Well get an ADCDONE2 interrupt
++/* issue a XY read command to the ADC of PCAP2. Well get an ADCDONE interrupt
+ * once the result of the conversion is available */
+static void pcap_ts_start_xy_read(struct pcap_ts *pcap_ts)
+{
+ u_int32_t tmp;
+
-+ ezx_pcap_read(SSP_PCAP_ADJ_ADC1_REGISTER, &tmp);
-+ tmp &= SSP_PCAP_ADC_START_VALUE_SET_MASK;
-+ tmp |= SSP_PCAP_ADC_START_VALUE;
-+ ezx_pcap_write(SSP_PCAP_ADJ_ADC1_REGISTER, tmp);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_ADC2_ASC, 1);
++ ezx_pcap_read(PCAP_REG_ADC1, &tmp);
++ tmp &= ~(PCAP_BIT_ADC1_RAND | PCAP_ADC1_ADA1_MASK |
++ PCAP_ADC1_ADA2_MASK);
++ tmp |= (PCAP_BIT_ADC1_ADEN | PCAP_BIT_ADC1_AD_SEL1 |
++ PCAP_BIT_ADC1_AD_SEL2 | (5 << PCAP_ADC1_ADA1_SHIFT) |
++ (3 << PCAP_ADC1_ADA2_SHIFT));
++ ezx_pcap_write(PCAP_REG_ADC1, tmp);
++ ezx_pcap_bit_set(PCAP_BIT_ADC2_ASC, 1);
+}
+
+/* read the XY result from the ADC of PCAP2 */
+{
+ u_int32_t tmp;
+
-+ ezx_pcap_read(SSP_PCAP_ADJ_ADC2_REGISTER, &tmp);
++ ezx_pcap_read(PCAP_REG_ADC2, &tmp);
+
-+ if (pcap_ts->read_state == COORDINATE && !(tmp & 0x00400000)) {
-+ pcap_ts->x = (tmp & SSP_PCAP_ADD1_VALUE_MASK);
-+ pcap_ts->y = (tmp & SSP_PCAP_ADD2_VALUE_MASK)
-+ >>SSP_PCAP_ADD2_VALUE_SHIFT;
++ if (pcap_ts->read_state == POSITION_XY_MEASUREMENT) {
++ pcap_ts->x = (tmp & PCAP_ADC2_ADD1_MASK) >>
++ PCAP_ADC2_ADD1_SHIFT;
++ pcap_ts->y = (tmp & PCAP_ADC2_ADD2_MASK) >>
++ PCAP_ADC2_ADD2_SHIFT;
+ } else {
-+ pcap_ts->pressure = (tmp & SSP_PCAP_ADD2_VALUE_MASK)
-+ >>SSP_PCAP_ADD2_VALUE_SHIFT;
++ pcap_ts->pressure = (tmp & PCAP_ADC2_ADD2_MASK) >>
++ PCAP_ADC2_ADD2_SHIFT;
+ }
-+
+}
+
+/* PCAP2 interrupts us when ADC conversion result is available */
+
+ pcap_ts_get_xy_value(pcap_ts);
+ DEBUGP(KERN_DEBUG "%s X=%4d, Y=%4d Z=%4d ",
-+ pcap_ts->read_state == COORDINATE ? "COORD" : "PRESS",
-+ pcap_ts->x, pcap_ts->y, pcap_ts->pressure);
-+
++ pcap_ts->read_state == POSITION_XY_MEASUREMENT ? "COORD" :
++ "PRESS", pcap_ts->x, pcap_ts->y, pcap_ts->pressure);
+ switch (pcap_ts->read_state) {
-+ case PRESSURE:
++ case PRESSURE_MEASUREMENT:
+ if (pcap_ts->pressure >= PRESSURE_MAX ||
+ pcap_ts->pressure <= PRESSURE_MIN ) {
+ /* pen has been released (or cant read pressure - WM)*/
+ input_report_abs(pcap_ts->input, ABS_PRESSURE, pcap_ts->pressure);
+ }
+ /* switch state machine into coordinate read mode */
-+ pcap_ts->read_state = COORDINATE;
-+ pcap_ts_mode(PCAP_TS_POSITION_XY_MEASUREMENT);
++ pcap_ts_mode(pcap_ts, POSITION_XY_MEASUREMENT);
+ pcap_ts_start_xy_read(pcap_ts);
+ break;
-+ case COORDINATE:
++ case POSITION_XY_MEASUREMENT:
+ if (pcap_ts->x <= X_AXIS_MIN || pcap_ts->x >= X_AXIS_MAX ||
+ pcap_ts->y <= Y_AXIS_MIN || pcap_ts->y >= Y_AXIS_MAX) {
+ /* pen has been released */
+
+ /* ask PCAP2 to interrupt us if touch event happens
+ * again */
-+ pcap_ts->read_state = STANDBY;
-+ pcap_ts_mode(PCAP_TS_STANDBY_MODE);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_MSR_TSM, 0);
++ pcap_ts_mode(pcap_ts, STANDBY_MODE);
++ enable_irq(pcap_ts->irq_touch);
+ } else {
+ DEBUGP("DOWN\n");
+ input_report_abs(pcap_ts->input, ABS_X, pcap_ts->x);
+ input_report_abs(pcap_ts->input, ABS_Y, pcap_ts->y);
+
+ /* switch back to pressure read mode */
-+ pcap_ts->read_state = PRESSURE;
-+ pcap_ts_mode(PCAP_TS_PRESSURE_MEASUREMENT);
++ pcap_ts_mode(pcap_ts, PRESSURE_MEASUREMENT);
+ mod_timer(&pcap_ts->timer, jiffies + SAMPLE_INTERVAL);
+ }
+ input_sync(pcap_ts->input);
+ DEBUGP("ERROR\n");
+ break;
+ }
-+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pcap_ts_irq_touch(int irq, void *dev_id)
+{
+ struct pcap_ts *pcap_ts = dev_id;
-+
+ /* mask Touchscreen interrupt bit, prevents further touch events
+ * from being reported to us until we're finished with reading
+ * both pressure and x/y from ADC */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_MSR_TSM, 1);
++ disable_irq(pcap_ts->irq_touch);
+
+ DEBUGP("touched!!\n");
-+ pcap_ts_mode(PCAP_TS_PRESSURE_MEASUREMENT);
-+ pcap_ts->read_state = PRESSURE;
++ pcap_ts_mode(pcap_ts, PRESSURE_MEASUREMENT);
+ pcap_ts_start_xy_read(pcap_ts);
-+
+ return IRQ_HANDLED;
+}
+
+
+static int __init ezxts_probe(struct platform_device *pdev)
+{
-+ int ret;
-+ u_int32_t tmp;
+ struct pcap_ts *pcap_ts;
+ struct input_dev *input_dev;
+ int err = -ENOMEM;
+ goto fail;
+ }
+
-+ // Some initialization before done in ssp_pcap_open()
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ADC1_TS_REFENB, 0);
-+ // ack interrupts
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ISR_ADCDONE2I, 1);
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ISR_TSI, 1);
-+ // unmask interrupts
-+ // ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_MSR_TSM, 0);
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_MSR_ADCDONE2M, 0);
-+ // set adc bits? FIXME I dont think its necessary - WM
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ADC2_ADINC1, 0);
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ADC2_ADINC2, 0);
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ADC1_ATO0, 0);
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ADC1_ATO1, 0);
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ADC1_ATO2, 0);
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ADC1_ATO3, 0);
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ADC1_ATOX, 0);
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ADC1_MTR1, 0);
-+ ezx_pcap_bit_set( SSP_PCAP_ADJ_BIT_ADC1_MTR2, 0);
-+
-+ ret = ezx_pcap_read(SSP_PCAP_ADJ_ADC1_REGISTER, &tmp);
-+ if (ret < 0)
-+ return ret;
-+
-+ tmp &= (~SSP_PCAP_TOUCH_PANEL_POSITION_DETECT_MODE_MASK);
-+ tmp |= PCAP_TS_STANDBY_MODE;
-+
-+ ret = ezx_pcap_write(SSP_PCAP_ADJ_ADC1_REGISTER, tmp);
-+ if (ret < 0)
-+ return ret;
++ ezx_pcap_bit_set(PCAP_BIT_ADC1_TS_REFENB, 0);
++ pcap_ts_mode(pcap_ts, STANDBY_MODE);
+
+ err = request_irq(pcap_ts->irq_xy, pcap_ts_irq_xy, SA_INTERRUPT,
+ "pcap-ts X/Y", pcap_ts);
+
+ platform_set_drvdata(pdev, pcap_ts);
+
-+ pcap_ts->read_state = STANDBY;
-+ pcap_ts_mode(PCAP_TS_STANDBY_MODE);
-+
-+ /* enable pressure interrupt */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_MSR_TSM, 0);
-+
+ input_dev->name = "pcap-touchscreen";
+ input_dev->phys = "ezxts/input0";
+ input_dev->id.bustype = BUS_HOST;
+
+static int ezxts_suspend(struct platform_device *dev, pm_message_t state)
+{
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_ADC1_TS_REF_LOWPWR, 1);
++ ezx_pcap_bit_set(PCAP_BIT_ADC1_TS_REF_LOWPWR, 1);
+ return 0;
+}
+
+static int ezxts_resume(struct platform_device *dev)
+{
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_ADC1_TS_REF_LOWPWR, 0);
++ ezx_pcap_bit_set(PCAP_BIT_ADC1_TS_REF_LOWPWR, 0);
+ /* just in case we suspend with TSI masked. */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_MSR_TSM, 0);
++// ezx_pcap_bit_set(PCAP_BIT_MSR_TSM, 0);
+ return 0;
+}
+
+MODULE_LICENSE("GPL");
Index: linux-2.6.21/drivers/input/touchscreen/Makefile
===================================================================
---- linux-2.6.21.orig/drivers/input/touchscreen/Makefile 2007-06-02 20:17:58.000000000 -0300
-+++ linux-2.6.21/drivers/input/touchscreen/Makefile 2007-06-02 20:18:40.000000000 -0300
+--- linux-2.6.21.orig/drivers/input/touchscreen/Makefile 2007-08-31 22:27:48.000000000 -0300
++++ linux-2.6.21/drivers/input/touchscreen/Makefile 2007-08-31 23:06:39.000000000 -0300
@@ -16,3 +16,4 @@
obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o
obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o
--- /dev/null
+Index: linux-2.6.21/drivers/usb/gadget/ether.c
+===================================================================
+--- linux-2.6.21.orig/drivers/usb/gadget/ether.c 2007-08-20 22:05:12.000000000 +0800
++++ linux-2.6.21/drivers/usb/gadget/ether.c 2007-08-20 22:06:25.000000000 +0800
+@@ -2697,10 +2697,16 @@
+ MODULE_LICENSE ("GPL");
+
+
+-static int __init init (void)
++// Alex add FIXME
++int usb_ether_init (void)
+ {
+ return usb_gadget_register_driver (ð_driver);
+ }
++
++static int __init init (void)
++{
++// return usb_gadget_register_driver (ð_driver);
++}
+ module_init (init);
+
+ static void __exit cleanup (void)
+Index: linux-2.6.21/drivers/usb/gadget/pxa27x_udc.c
+===================================================================
+--- linux-2.6.21.orig/drivers/usb/gadget/pxa27x_udc.c 2007-08-20 22:07:31.000000000 +0800
++++ linux-2.6.21/drivers/usb/gadget/pxa27x_udc.c 2007-08-20 22:07:47.000000000 +0800
+@@ -2227,6 +2227,8 @@
+ udc_init_ep(udc);
+ udc_reinit(udc);
+
++ usb_ether_init(); // Alex add FIXME
++
+ /* irq setup after old hardware state is cleaned up */
+ retval = request_irq(IRQ_USB, pxa27x_udc_irq,
+ SA_INTERRUPT, driver_name, udc);
HOMEPAGE = "http://www.openezx.org"
LICENSE = "GPL"
EZX = "ezxdev"
-PR = "${EZX}-r9"
+PR = "${EZX}-r10"
inherit kernel
file://patches/a780-ts.patch;patch=1 \
file://patches/e680-ts.patch;patch=1 \
file://patches/a1200-ts.patch;patch=1 \
+ file://patches/ezx-eoc.patch;patch=1 \
+ file://patches/a1200-eoc.patch;patch=1 \
file://patches/ezx-backlight.patch;patch=1 \
file://patches/a780-flip.patch;patch=1 \
file://patches/e680-locksw.patch;patch=1 \
file://patches/mux-fix-tty-driver.patch;patch=1 \
file://patches/mux-linux-2.6.21-fix.patch;patch=1 \
file://patches/asoc-pxa-ssp.patch;patch=1 \
- http://shell.studenti.unina.it/~ospite/tmp/ezx-asoc-preview.patch;patch=1 \
+ file://patches/asoc-fix-loopback.patch;patch=1 \
+ file://patches/ezx-asoc.patch;patch=1 \
file://defconfig \
\
"
git.openpandora.org / openembedded.git / commitdiff