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clk: tegra124: Add PLL_M_UD and PLL_C_UD clocks
authorMikko Perttunen <mperttunen@nvidia.com>
Fri, 11 Jul 2014 14:18:29 +0000 (17:18 +0300)
committerPeter De Schrijver <pdeschrijver@nvidia.com>
Thu, 18 Sep 2014 10:57:12 +0000 (13:57 +0300)
These clocks are used as parents for some EMC timings.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>

No differences found
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