ARM: MM: Add DT binding for Feroceon L2 cache

Instantiate the L2 cache from DT. Indicate in DT where the cache
control register is so that it is possible to enable/disable write
through on the CPU.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt
new file mode 100644 (file)
index 0000000..0d244b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt
@@ -0,0 +1,16 @@
+* Marvell Feroceon Cache
+
+Required properties:
+- compatible : Should be either "marvell,feroceon-cache" or
+              "marvell,kirkwood-cache".
+
+Optional properties:
+- reg        : Address of the L2 cache control register. Mandatory for
+              "marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
+
+
+Example:
+               l2: l2-cache@20128 {
+                       compatible = "marvell,kirkwood-cache";
+                       reg = <0x20128 0x4>;
+               };

diff --cc arch/arm/include/asm/hardware/cache-feroceon-l2.h
Simple merge

diff --cc arch/arm/mach-kirkwood/board-dt.c
Simple merge

diff --cc arch/arm/mm/cache-feroceon-l2.c
Simple merge