drm/i915: Kill pipestat[] cache
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 20 Feb 2013 19:16:18 +0000 (21:16 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 21 Feb 2013 13:01:12 +0000 (14:01 +0100)
Caching the PIPESTAT enable bits has been deemed pointless. Just
read them from the register itself.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_irq.c

Simple merge
Simple merge