mach-k3: use minimal memory map for all K3

The K3 family of SoCs encompasses a wide variety of devices with varying
DDR configurations and memory carveout requirements, the current static
memory map provides basic support for TI EVMs but does not scale well
for newer platforms (such as AM62SiP with 512MiB of RAM).

Therefore this patch replaces the existing memory map with a minimal
one, that could be more easily modified at runtime.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>

diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c
index 0e07b1b..79650a7 100644 (file)
--- a/arch/arm/mach-k3/arm64/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64/arm64-mmu.c
@@ -11,42 +11,30 @@
 
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
 
 struct mm_region k3_mem_map[] = {
-       {
+       { /* SoC Peripherals */
                .virt = 0x0UL,
                .phys = 0x0UL,
                .size = 0x80000000UL,
                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
                         PTE_BLOCK_NON_SHARE |
                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       }, {
-               .virt = 0x80000000UL,
-               .phys = 0x80000000UL,
-               .size = 0x1e780000UL,
-               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-                        PTE_BLOCK_INNER_SHARE
-       }, {
-               .virt = 0xa0000000UL,
-               .phys = 0xa0000000UL,
-               .size = 0x60000000UL,
-               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-                        PTE_BLOCK_INNER_SHARE
-       }, {
-               .virt = 0x880000000UL,
-               .phys = 0x880000000UL,
-               .size = 0x80000000UL,
-               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-                        PTE_BLOCK_INNER_SHARE
-       }, {
+       }, { /* Flash Peripherals */
                .virt = 0x500000000UL,
                .phys = 0x500000000UL,
                .size = 0x380000000UL,
                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
                         PTE_BLOCK_NON_SHARE |
                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       }, {
-               /* List terminator */
+       }, { /* First DRAM Bank of size 2G */
+               .virt = CFG_SYS_SDRAM_BASE,
+               .phys = CFG_SYS_SDRAM_BASE,
+               .size = SZ_2G,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, { /* List terminator */
                0,
        }
 };