pinctrl: sunxi: add new D1 pinctrl support

For the first time since at least the Allwinner A10 SoCs, the D1 (and
related cores) use a new pincontroller MMIO register layout, so we
cannot use our hardcoded, fixed offsets anymore.
Ideally this would all be handled by devicetree and DM drivers, but for
the DT-less SPL we still need the legacy interfaces.

Add a new Kconfig symbol to differenciate between the two generations of
pincontrollers, and just use that to just switch some basic symbols.
The rest is already abstracted enough, so works out of the box.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 74baa98..ba42b07 100644 (file)
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -372,6 +372,13 @@ config SUNXI_GPIO
        help
          Support the GPIO device in Allwinner SoCs.
 
+config SUNXI_NEW_PINCTRL
+       bool
+       depends on SUNXI_GPIO
+       ---help---
+       The Allwinner D1 and other new SoCs use a different register map
+       for the GPIO block, which we need to know about in the SPL.
+
 config XILINX_GPIO
        bool "Xilinx GPIO driver"
        depends on DM_GPIO

diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index e335496..e4463a2 100644 (file)
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -40,10 +40,23 @@
 #define GPIO_DAT_REG_OFFSET    0x10
 
 #define GPIO_DRV_REG_OFFSET    0x14
-#define GPIO_DRV_INDEX(pin)    (((pin) & 0x1f) >> 4)
-#define GPIO_DRV_OFFSET(pin)   ((((pin) & 0x1f) & 0xf) << 1)
+
+/*             Newer SoCs use a slightly different register layout */
+#ifdef CONFIG_SUNXI_NEW_PINCTRL
+/* pin drive strength: 4 bits per pin */
+#define GPIO_DRV_INDEX(pin)    ((pin) / 8)
+#define GPIO_DRV_OFFSET(pin)   (((pin) % 8) * 4)
+
+#define GPIO_PULL_REG_OFFSET   0x24
+
+#else /* older generation pin controllers */
+/* pin drive strength: 2 bits per pin */
+#define GPIO_DRV_INDEX(pin)    ((pin) / 16)
+#define GPIO_DRV_OFFSET(pin)   (((pin) % 16) * 2)
 
 #define GPIO_PULL_REG_OFFSET   0x1c
+#endif
+
 #define GPIO_PULL_INDEX(pin)   (((pin) & 0x1f) >> 4)
 #define GPIO_PULL_OFFSET(pin)  ((((pin) & 0x1f) & 0xf) << 1)
 

diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index c1fdf7e..30d8879 100644 (file)
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -62,7 +62,6 @@
 #define SUN50I_H6_GPIO_POW_MOD_VAL     0x348
 
 #define SUNXI_GPIOS_PER_BANK   32
-#define SUNXI_PINCTRL_BANK_SIZE 0x24
 
 #define SUNXI_GPIO_NEXT(__gpio) \
        ((__gpio##_START) + SUNXI_GPIOS_PER_BANK)
@@ -102,7 +101,6 @@ enum sunxi_gpio_number {
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT       0
 #define SUNXI_GPIO_OUTPUT      1
-#define SUNXI_GPIO_DISABLE     7
 
 #define SUN8I_H3_GPA_UART0     2
 #define SUN8I_H3_GPA_UART2     2
@@ -171,6 +169,14 @@ enum sunxi_gpio_number {
 
 #define SUN9I_GPN_R_RSB                3
 
+#ifdef CONFIG_SUNXI_NEW_PINCTRL
+       #define SUNXI_PINCTRL_BANK_SIZE 0x30
+       #define SUNXI_GPIO_DISABLE      0xf
+#else
+       #define SUNXI_PINCTRL_BANK_SIZE 0x24
+       #define SUNXI_GPIO_DISABLE      0x7
+#endif
+
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE        0
 #define SUNXI_GPIO_PULL_UP     1