arm64: versal2: Add PL bit stream load support
authorPrasad Kummari <prasad.kummari@amd.com>
Thu, 27 Mar 2025 10:51:59 +0000 (16:21 +0530)
committerMichal Simek <michal.simek@amd.com>
Wed, 16 Apr 2025 11:44:44 +0000 (13:44 +0200)
Add support for loading the secure & non-secure pdi images and PL
bitstream on the Versal Gen2 platform. The FPGA driver is enabled
to load the bitstream in PDI format on the AMD Versal Gen2 device.
PDI is the new programmable device image format for Versal Gen2,
and the bitstream for the Versal Gen2 platform is generated exclusively
in this format.

With the enhanced SMC format in TF-A ensuring transparent payload
forwarding for Versal Gen2, the u-boot driver must now handle the
word swapping of PDI address that was previously done in TF-A for
this API. The source code for the Versal2 loadpdi command and the
CONFIG_CMD_VERSAL2 configuration has been removed. It now utilizes
the fpga load <dev> <address> <length> command to load secure &
non-secure pdi images.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Link: https://lore.kernel.org/r/20250327105200.1262615-3-prasad.kummari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
arch/arm/mach-versal2/Kconfig
board/amd/versal2/Kconfig [deleted file]
board/amd/versal2/Makefile
board/amd/versal2/board.c
board/amd/versal2/cmds.c [deleted file]
configs/amd_versal2_virt_defconfig
drivers/fpga/versalpl.c
include/xilinx.h

index 3f18e33..2a59515 100644 (file)
@@ -50,6 +50,5 @@ config ZYNQ_SDHCI_MAX_FREQ
        default 200000000
 
 source "board/xilinx/Kconfig"
-source "board/amd/versal2/Kconfig"
 
 endif
diff --git a/board/amd/versal2/Kconfig b/board/amd/versal2/Kconfig
deleted file mode 100644 (file)
index ab46af6..0000000
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2020 - 2022, Xilinx, Inc.
-# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
-#
-if ARCH_VERSAL2
-
-config CMD_VERSAL2
-       bool "Enable Versal Gen 2 specific commands"
-       default y
-       depends on ZYNQMP_FIRMWARE
-       help
-         Select this to enable AMD Versal Gen 2 specific commands.
-         Commands like versal2 loadpdi are enabled by this.
-
-endif
index 3a04451..1673be4 100644 (file)
@@ -8,4 +8,3 @@
 
 obj-y  := board.o
 
-obj-$(CONFIG_CMD_VERSAL2)   += cmds.o
index c99620d..aea3bf0 100644 (file)
@@ -20,6 +20,7 @@
 #include <asm/arch/sys_proto.h>
 #include <dm/device.h>
 #include <dm/uclass.h>
+#include <versalpl.h>
 #include "../../xilinx/common/board.h"
 
 #include <linux/bitfield.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = {
+       xilinx_versal2, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
+       FPGA_LEGACY
+};
+#endif
+
 int board_init(void)
 {
        printf("EL Level:\tEL%d\n", current_el());
 
+#if defined(CONFIG_FPGA_VERSALPL)
+       fpga_init();
+       fpga_add(fpga_xilinx, &versalpl);
+#endif
+
        return 0;
 }
 
diff --git a/board/amd/versal2/cmds.c b/board/amd/versal2/cmds.c
deleted file mode 100644 (file)
index 56ae39b..0000000
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2024, Advanced Micro Devices, Inc.
- *
- * Michal Simek <michal.simek@amd.com>
- */
-
-#include <cpu_func.h>
-#include <command.h>
-#include <log.h>
-#include <memalign.h>
-#include <versalpl.h>
-#include <vsprintf.h>
-#include <zynqmp_firmware.h>
-
-/**
- * do_versal2_load_pdi - Handle the "versal2 load pdi" command-line command
- * @cmdtp:      Command data struct pointer
- * @flag:       Command flag
- * @argc:       Command-line argument count
- * @argv:       Array of command-line arguments
- *
- * Processes the versal2 load pdi command
- *
- * Return: return 0 on success, Error value if command fails.
- * CMD_RET_USAGE incase of incorrect/missing parameters.
- */
-static int do_versal2_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
-                              char * const argv[])
-{
-       u32 buf_lo, buf_hi;
-       u32 ret_payload[PAYLOAD_ARG_CNT];
-       ulong addr, *pdi_buf;
-       size_t len;
-       int ret;
-
-       if (argc != cmdtp->maxargs) {
-               debug("pdi_load: incorrect parameters passed\n");
-               return CMD_RET_USAGE;
-       }
-
-       addr = simple_strtol(argv[1], NULL, 16);
-       if (!addr) {
-               debug("pdi_load: zero pdi_data address\n");
-               return CMD_RET_USAGE;
-       }
-
-       len = hextoul(argv[2], NULL);
-       if (!len) {
-               debug("pdi_load: zero size\n");
-               return CMD_RET_USAGE;
-       }
-
-       pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
-       if ((ulong)addr != (ulong)pdi_buf) {
-               memcpy((void *)pdi_buf, (void *)addr, len);
-               debug("Pdi addr:0x%lx aligned to 0x%lx\n",
-                     addr, (ulong)pdi_buf);
-       }
-
-       flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
-
-       buf_lo = lower_32_bits((ulong)pdi_buf);
-       buf_hi = upper_32_bits((ulong)pdi_buf);
-
-       ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
-                               buf_hi, 0, ret_payload);
-       if (ret)
-               printf("PDI load failed with err: 0x%08x\n", ret);
-
-       return cmd_process_error(cmdtp, ret);
-}
-
-U_BOOT_LONGHELP(versal2,
-       "loadpdi addr len - Load pdi image\n"
-       "load pdi image at ddr address 'addr' with pdi image size 'len'\n");
-
-U_BOOT_CMD_WITH_SUBCMDS(versal2, "Versal Gen 2 sub-system", versal2_help_text,
-                       U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1,
-                                           do_versal2_load_pdi));
index 087c7f0..6946b2b 100644 (file)
@@ -72,6 +72,8 @@ CONFIG_CLK_CCF=y
 CONFIG_CLK_SCMI=y
 CONFIG_DFU_RAM=y
 CONFIG_ARM_FFA_TRANSPORT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_VERSALPL=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_I2C_MUX=y
index 1957e8d..d691f13 100644 (file)
@@ -41,8 +41,15 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
        buf_lo = lower_32_bits(bin_buf);
        buf_hi = upper_32_bits(bin_buf);
 
-       ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
-                               buf_hi, 0, ret_payload);
+
+       if (desc->family == xilinx_versal2) {
+               ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_hi,
+                                       buf_lo, 0, ret_payload);
+       } else {
+               ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+                                       buf_hi, 0, ret_payload);
+       }
+
        if (ret)
                printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
 
index 2b4d6c9..c54d6dc 100644 (file)
@@ -35,6 +35,7 @@ typedef enum {                        /* typedef xilinx_family */
        xilinx_zynqmp,          /* ZynqMP Family */
        xilinx_versal,          /* Versal Family */
        xilinx_versal_net,      /* Versal NET Family */
+       xilinx_versal2,         /* Versal Gen 2 Family */
        max_xilinx_type         /* insert all new types before this */
 } xilinx_family;               /* end, typedef xilinx_family */