xilinx: mbv: Add missing mmu-type cpu property

OpenSBI expects mmu-type to be present in DT that's why add it. Without it
OpenSBI disable CPU node which ends up in not working boot.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 4050ce2..96e4280 100644 (file)
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for AMD MicroBlaze V
  *
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -26,6 +26,7 @@
                        device_type = "cpu";
                        reg = <0>;
                        riscv,isa = "rv32imafdc";
+                       mmu-type = "riscv,sv39";
                        i-cache-size = <32768>;
                        d-cache-size = <32768>;
                        clock-frequency = <100000000>;

diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
index 4d65d33..5a989c1 100644 (file)
--- a/arch/riscv/dts/xilinx-mbv64.dts
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for AMD MicroBlaze V
  *
- * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -26,6 +26,7 @@
                        device_type = "cpu";
                        reg = <0>;
                        riscv,isa = "rv64imafdc";
+                       mmu-type = "riscv,sv39";
                        i-cache-size = <32768>;
                        d-cache-size = <32768>;
                        clock-frequency = <100000000>;