ram: k3-ddrss: Enable ECC interrupts

Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>

diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 0678db3..e4f9891 100644 (file)
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -45,6 +45,11 @@
 #define DDRSS_ECC_R2_STR_ADDR_REG              0x0140
 #define DDRSS_ECC_R2_END_ADDR_REG              0x0144
 #define DDRSS_ECC_1B_ERR_CNT_REG               0x0150
+#define DDRSS_V2A_INT_SET_REG                  0x00a8
+
+#define DDRSS_V2A_INT_SET_REG_ECC1BERR_EN      BIT(3)
+#define DDRSS_V2A_INT_SET_REG_ECC2BERR_EN      BIT(4)
+#define DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN     BIT(5)
 
 #define SINGLE_DDR_SUBSYSTEM   0x1
 #define MULTI_DDR_SUBSYSTEM    0x2
@@ -742,6 +747,9 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
        /* Clear Error Count Register */
        writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG);
 
+       writel(DDRSS_V2A_INT_SET_REG_ECC1BERR_EN | DDRSS_V2A_INT_SET_REG_ECC2BERR_EN |
+                  DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN, base + DDRSS_V2A_INT_SET_REG);
+
        /* Enable ECC Check */
        val = readl(base + DDRSS_ECC_CTRL_REG);
        val |= DDRSS_ECC_CTRL_REG_ECC_CK;