arm: dts: k3: Remove leftover file after OF_UPSTREAM

The file k3-am62a7.dtsi is part of upstream DT and should
have been removed when migrating to OF_UPSTREAM but must
have been missed. Do this here.

Signed-off-by: Andrew Davis <afd@ti.com>

diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi
deleted file mode 100644 (file)
index f86a234..0000000
--- a/arch/arm/dts/k3-am62a7.dtsi
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62A7 SoC family in Quad core configuration
- *
- * TRM: https://www.ti.com/lit/zip/spruj16
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-am62a.dtsi"
-
-/ {
-       cpus {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               cpu-map {
-                       cluster0: cluster0 {
-                               core0 {
-                                       cpu = <&cpu0>;
-                               };
-
-                               core1 {
-                                       cpu = <&cpu1>;
-                               };
-
-                               core2 {
-                                       cpu = <&cpu2>;
-                               };
-
-                               core3 {
-                                       cpu = <&cpu3>;
-                               };
-                       };
-               };
-
-               cpu0: cpu@0 {
-                       compatible = "arm,cortex-a53";
-                       reg = <0x000>;
-                       device_type = "cpu";
-                       enable-method = "psci";
-                       i-cache-size = <0x8000>;
-                       i-cache-line-size = <64>;
-                       i-cache-sets = <256>;
-                       d-cache-size = <0x8000>;
-                       d-cache-line-size = <64>;
-                       d-cache-sets = <128>;
-                       next-level-cache = <&L2_0>;
-               };
-
-               cpu1: cpu@1 {
-                       compatible = "arm,cortex-a53";
-                       reg = <0x001>;
-                       device_type = "cpu";
-                       enable-method = "psci";
-                       i-cache-size = <0x8000>;
-                       i-cache-line-size = <64>;
-                       i-cache-sets = <256>;
-                       d-cache-size = <0x8000>;
-                       d-cache-line-size = <64>;
-                       d-cache-sets = <128>;
-                       next-level-cache = <&L2_0>;
-               };
-
-               cpu2: cpu@2 {
-                       compatible = "arm,cortex-a53";
-                       reg = <0x002>;
-                       device_type = "cpu";
-                       enable-method = "psci";
-                       i-cache-size = <0x8000>;
-                       i-cache-line-size = <64>;
-                       i-cache-sets = <256>;
-                       d-cache-size = <0x8000>;
-                       d-cache-line-size = <64>;
-                       d-cache-sets = <128>;
-                       next-level-cache = <&L2_0>;
-               };
-
-               cpu3: cpu@3 {
-                       compatible = "arm,cortex-a53";
-                       reg = <0x003>;
-                       device_type = "cpu";
-                       enable-method = "psci";
-                       i-cache-size = <0x8000>;
-                       i-cache-line-size = <64>;
-                       i-cache-sets = <256>;
-                       d-cache-size = <0x8000>;
-                       d-cache-line-size = <64>;
-                       d-cache-sets = <128>;
-                       next-level-cache = <&L2_0>;
-               };
-       };
-
-       L2_0: l2-cache0 {
-               compatible = "cache";
-               cache-unified;
-               cache-level = <2>;
-               cache-size = <0x80000>;
-               cache-line-size = <64>;
-               cache-sets = <512>;
-       };
-};