clk: qcom: Move qcom_gate_clk_en() to C file

This avoids having to inline it separately into every single clock driver,
when U-Boot is built with support for multiple SoCs.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-2-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>

diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 7687bbe..5018851 100644 (file)
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -74,6 +74,21 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
        } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
 }
 
+int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
+{
+       u32 val;
+       if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
+               log_err("gcc@%#08llx: unknown clock ID %lu!\n",
+                       priv->base, id);
+               return -ENOENT;
+       }
+
+       val = readl(priv->base + priv->data->clks[id].reg);
+       writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
+
+       return 0;
+}
+
 #define APPS_CMD_RCGR_UPDATE BIT(0)
 
 /* Update clock command via CMD_RCGR */

diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index f43edea..ee0347d 100644 (file)
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -107,19 +107,6 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
                      int source);
 void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
 
-static inline int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
-{
-       u32 val;
-       if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
-               log_err("gcc@%#08llx: unknown clock ID %lu!\n",
-                       priv->base, id);
-               return -ENOENT;
-       }
-
-       val = readl(priv->base + priv->data->clks[id].reg);
-       writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
-
-       return 0;
-}
+int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id);
 
 #endif