arm: dts: mediatek: add pcie support for mt7988

This patch adds PCIe support for mt7988

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts
index 71a58a2..14274e2 100644 (file)
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -63,6 +63,24 @@
        };
 };
 
+&pcie0 {
+       status = "okay";
+};
+
+&pcie1 {
+       status = "okay";
+};
+
+/* PCIE2 not working in u-boot */
+&pcie2 {
+       status = "disabled";
+};
+
+/* PCIE3 not working in u-boot */
+&pcie3 {
+       status = "disabled";
+};
+
 &pinctrl {
        i2c1_pins: i2c1-pins {
                mux {

diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index e120e50..6196ac1 100644 (file)
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -188,6 +188,152 @@
                status = "okay";
        };
 
+       pcie2: pcie@11280000 {
+               compatible = "mediatek,mt7988-pcie",
+                            "mediatek,mt7986-pcie",
+                            "mediatek,mt8192-pcie";
+               device_type = "pci";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               reg = <0 0x11280000 0 0x2000>;
+               reg-names = "pcie-mac";
+               linux,pci-domain = <3>;
+               interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+               bus-range = <0x00 0xff>;
+               ranges = <0x82000000 0 0x20200000 0 0x20200000 0 0x07e00000>;
+               clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+                        <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+                        <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+                        <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+               clock-names = "pl_250m", "tl_26m", "peri_26m",
+                             "top_133m";
+               phys = <&xphyu3port0 PHY_TYPE_PCIE>;
+               phy-names = "pcie-phy";
+
+               status = "disabled";
+
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 0x7>;
+               interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+                               <0 0 0 2 &pcie_intc2 1>,
+                               <0 0 0 3 &pcie_intc2 2>,
+                               <0 0 0 4 &pcie_intc2 3>;
+
+               pcie_intc2: interrupt-controller {
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       interrupt-controller;
+               };
+       };
+
+       pcie3: pcie@11290000 {
+               compatible = "mediatek,mt7988-pcie",
+                            "mediatek,mt7986-pcie",
+                            "mediatek,mt8192-pcie";
+               device_type = "pci";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               reg = <0 0x11290000 0 0x2000>;
+               reg-names = "pcie-mac";
+               linux,pci-domain = <2>;
+               interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+               bus-range = <0x00 0xff>;
+               ranges = <0x82000000 0 0x28200000 0 0x28200000 0 0x07e00000>;
+               clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+                        <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+                        <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+                        <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+               clock-names = "pl_250m", "tl_26m", "peri_26m",
+                             "top_133m";
+               use-dedicated-phy;
+
+               status = "disabled";
+
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 0x7>;
+               interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+                               <0 0 0 2 &pcie_intc3 1>,
+                               <0 0 0 3 &pcie_intc3 2>,
+                               <0 0 0 4 &pcie_intc3 3>;
+               pcie_intc3: interrupt-controller {
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       interrupt-controller;
+               };
+       };
+
+       pcie0: pcie@11300000 {
+               compatible = "mediatek,mt7988-pcie",
+                            "mediatek,mt7986-pcie",
+                            "mediatek,mt8192-pcie";
+               device_type = "pci";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               reg = <0 0x11300000 0 0x2000>;
+               reg-names = "pcie-mac";
+               linux,pci-domain = <0>;
+               interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+               bus-range = <0x00 0xff>;
+               ranges = <0x82000000 0 0x30200000 0 0x30200000 0 0x07e00000>;
+               clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+                        <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+                        <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+                        <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+               clock-names = "pl_250m", "tl_26m", "peri_26m",
+                             "top_133m";
+               use-dedicated-phy;
+
+               status = "disabled";
+
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 0x7>;
+               interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+                               <0 0 0 2 &pcie_intc0 1>,
+                               <0 0 0 3 &pcie_intc0 2>,
+                               <0 0 0 4 &pcie_intc0 3>;
+               pcie_intc0: interrupt-controller {
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       interrupt-controller;
+               };
+       };
+
+       pcie1: pcie@11310000 {
+               compatible = "mediatek,mt7988-pcie",
+                            "mediatek,mt7986-pcie",
+                            "mediatek,mt8192-pcie";
+               device_type = "pci";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               reg = <0 0x11310000 0 0x2000>;
+               reg-names = "pcie-mac";
+               linux,pci-domain = <1>;
+               interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+               bus-range = <0x00 0xff>;
+               ranges = <0x82000000 0 0x38200000 0 0x38200000 0 0x07e00000>;
+               clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+                        <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+                        <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+                        <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+               clock-names = "pl_250m", "tl_26m", "peri_26m",
+                             "top_133m";
+               use-dedicated-phy;
+
+               status = "disabled";
+
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 0x7>;
+               interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+                               <0 0 0 2 &pcie_intc1 1>,
+                               <0 0 0 3 &pcie_intc1 2>,
+                               <0 0 0 4 &pcie_intc1 3>;
+               pcie_intc1: interrupt-controller {
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       interrupt-controller;
+               };
+       };
+
        usbtphy: usb-phy@11c50000 {
                compatible = "mediatek,mt7988",
                             "mediatek,generic-tphy-v2";
@@ -215,6 +361,22 @@
                };
        };
 
+       xphy: xphy@11e10000 {
+               compatible = "mediatek,mt7988", "mediatek,xsphy";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               status = "disabled";
+
+               xphyu3port0: usb-phy@11e13000 {
+                       reg = <0 0x11e13400 0 0x500>;
+                       clocks = <&dummy_clk>;
+                       clock-names = "ref";
+                       #phy-cells = <1>;
+                       status = "okay";
+               };
+       };
+
        xfi_pextp0: syscon@11f20000 {
                compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
                reg = <0 0x11f20000 0 0x10000>;