--- /dev/null
+From fc313d72cbfd788f23a7623d0b8cd9c2af329b7b Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Wed, 10 Feb 2010 13:39:40 -0800
+Subject: [PATCH 01/37] OMAP3: enable i2c bus switching for Beagle and Overo
+
+---
+ drivers/i2c/omap24xx_i2c.c | 6 ++++++
+ include/configs/omap3_beagle.h | 1 +
+ include/configs/omap3_overo.h | 1 +
+ 3 files changed, 8 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
+index ff18991..30a8b4c 100644
+--- a/drivers/i2c/omap24xx_i2c.c
++++ b/drivers/i2c/omap24xx_i2c.c
+@@ -435,3 +435,9 @@ int i2c_set_bus_num(unsigned int bus)
+
+ return 0;
+ }
++
++int i2c_get_bus_num(void)
++{
++ return (int) current_bus;
++}
++
+diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
+index 08d79ac..87e3dd0 100644
+--- a/include/configs/omap3_beagle.h
++++ b/include/configs/omap3_beagle.h
+@@ -146,6 +146,7 @@
+ #define CONFIG_SYS_I2C_BUS 0
+ #define CONFIG_SYS_I2C_BUS_SELECT 1
+ #define CONFIG_DRIVER_OMAP34XX_I2C 1
++#define CONFIG_I2C_MULTI_BUS 1
+
+ /*
+ * TWL4030
+diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
+index a43500b..0d24758 100644
+--- a/include/configs/omap3_overo.h
++++ b/include/configs/omap3_overo.h
+@@ -117,6 +117,7 @@
+ #define CONFIG_SYS_I2C_BUS 0
+ #define CONFIG_SYS_I2C_BUS_SELECT 1
+ #define CONFIG_DRIVER_OMAP34XX_I2C 1
++#define CONFIG_I2C_MULTI_BUS 1
+
+ /*
+ * TWL4030
+--
+1.6.6.1
+
--- /dev/null
+From 59c9245c9a52954c8c084e257bbe55443201614b Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Wed, 10 Feb 2010 14:40:56 -0800
+Subject: [PATCH 02/37] OMAP3: add board revision detection for Overo
+
+---
+ board/overo/overo.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ board/overo/overo.h | 43 +++++++++++++++++++++---
+ 2 files changed, 127 insertions(+), 6 deletions(-)
+
+diff --git a/board/overo/overo.c b/board/overo/overo.c
+index e85be7d..3df1a12 100644
+--- a/board/overo/overo.c
++++ b/board/overo/overo.c
+@@ -61,11 +61,101 @@ int board_init(void)
+ }
+
+ /*
++ * Routine: get_sdio2_config
++ * Description: Return information about the wifi module connection
++ * Returns 0 if the module connects though a level translator
++ * Returns 1 if the module connects directly
++ */
++int get_sdio2_config(void) {
++ int sdio_direct;
++
++ if (!omap_request_gpio(130) && !omap_request_gpio(139)){
++
++ omap_set_gpio_direction(130, 0);
++ omap_set_gpio_direction(139, 1);
++
++ sdio_direct = 1;
++ omap_set_gpio_dataout(130, 0);
++ if (omap_get_gpio_datain(139) == 0) {
++ omap_set_gpio_dataout(130, 1);
++ if (omap_get_gpio_datain(139) == 1)
++ sdio_direct = 0;
++ }
++
++ omap_free_gpio(130);
++ omap_free_gpio(139);
++ } else {
++ printf("Error: unable to acquire sdio2 clk GPIOs\n");
++ sdio_direct=-1;
++ }
++
++ return sdio_direct;
++}
++
++/*
++ * Routine: get_board_revision
++ * Description: Returns the board revision
++ */
++int get_board_revision(void) {
++ int revision;
++
++ if (!omap_request_gpio(126) && !omap_request_gpio(127) &&
++ !omap_request_gpio(128) && !omap_request_gpio(129)){
++
++ omap_set_gpio_direction(126, 1);
++ omap_set_gpio_direction(127, 1);
++ omap_set_gpio_direction(128, 1);
++ omap_set_gpio_direction(129, 1);
++
++ revision = 0;
++ if (omap_get_gpio_datain(126) == 0)
++ revision += 1;
++ if (omap_get_gpio_datain(127) == 0)
++ revision += 2;
++ if (omap_get_gpio_datain(128) == 0)
++ revision += 4;
++ if (omap_get_gpio_datain(129) == 0)
++ revision += 8;
++
++ omap_free_gpio(126);
++ omap_free_gpio(127);
++ omap_free_gpio(128);
++ omap_free_gpio(129);
++ } else {
++ printf("Error: unable to acquire board revision GPIOs\n");
++ revision=-1;
++ }
++
++ return revision;
++}
++
++/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+ int misc_init_r(void)
+ {
++ printf("Board revision: ");
++ switch (get_board_revision()) {
++ case 0:
++ case 1:
++ switch (get_sdio2_config()) {
++ case 0:
++ printf(" 0\n");
++ MUX_OVERO_SDIO2_TRANSCEIVER();
++ break;
++ case 1:
++ printf(" 1\n");
++ MUX_OVERO_SDIO2_DIRECT();
++ break;
++ default:
++ printf(" unknown\n");
++ }
++ break;
++ default:
++ printf(" unsupported\n");
++ }
++
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+diff --git a/board/overo/overo.h b/board/overo/overo.h
+index 1873523..e120e09 100644
+--- a/board/overo/overo.h
++++ b/board/overo/overo.h
+@@ -206,12 +206,12 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
++ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\
++ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
++ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
++ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/\
+ /*Wireless LAN */\
+- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
++ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+@@ -220,7 +220,7 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
+- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
++ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+@@ -387,5 +387,36 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
++#define MUX_OVERO_SDIO2_DIRECT() \
++ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
++ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
++ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
++ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
++ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
++ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
++ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M0)) /*MMC2_DAT4*/\
++ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M0)) /*MMC2_DAT5*/\
++ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M0)) /*MMC2_DAT6*/\
++ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
++ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\
++ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
++ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
++ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
++
++#define MUX_OVERO_SDIO2_TRANSCEIVER() \
++ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
++ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
++ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
++ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
++ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
++ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
++ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
++ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
++ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
++ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
++ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\
++ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
++ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
++ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
+
+ #endif
+--
+1.6.6.1
+
--- /dev/null
+From 9db5da6e8a0d6fb973b71902525ad3298faa39d9 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Wed, 10 Feb 2010 14:51:48 -0800
+Subject: [PATCH 03/37] OMAP3: update Beagle revision detection to recognize C4 boards
+
+---
+ board/ti/beagle/beagle.c | 77 +++++++++++++++++++++++++++-------------------
+ board/ti/beagle/beagle.h | 7 +++-
+ 2 files changed, 51 insertions(+), 33 deletions(-)
+
+diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
+index 3b4c9e7..ba16dd7 100644
+--- a/board/ti/beagle/beagle.c
++++ b/board/ti/beagle/beagle.c
+@@ -38,7 +38,7 @@
+ #include <asm/mach-types.h>
+ #include "beagle.h"
+
+-static int beagle_revision_c;
++static int beagle_revision;
+
+ /*
+ * Routine: board_init
+@@ -60,41 +60,38 @@ int board_init(void)
+ /*
+ * Routine: beagle_get_revision
+ * Description: Return the revision of the BeagleBoard this code is running on.
+- * If it is a revision Ax/Bx board, this function returns 0,
+- * on a revision C board you will get a 1.
+ */
+ int beagle_get_revision(void)
+ {
+- return beagle_revision_c;
++ return beagle_revision;
+ }
+
+ /*
+ * Routine: beagle_identify
+- * Description: Detect if we are running on a Beagle revision Ax/Bx or
+- * Cx. This can be done by GPIO_171. If this is low, we are
+- * running on a revision C board.
++ * Description: Detect if we are running on a Beagle revision Ax/Bx,
++ * C1/2/3, C4 or D. This can be done by reading
++ * the level of GPIO173, GPIO172 and GPIO171. This should
++ * result in
++ * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
++ * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
++ * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
++ * GPIO173, GPIO172, GPIO171: 0 0 0 => D
+ */
+ void beagle_identify(void)
+ {
+- beagle_revision_c = 0;
+- if (!omap_request_gpio(171)) {
+- unsigned int val;
+-
+- omap_set_gpio_direction(171, 1);
+- val = omap_get_gpio_datain(171);
+- omap_free_gpio(171);
+-
+- if (val)
+- beagle_revision_c = 0;
+- else
+- beagle_revision_c = 1;
+- }
+-
+- printf("Board revision ");
+- if (beagle_revision_c)
+- printf("C\n");
+- else
+- printf("Ax/Bx\n");
++ omap_request_gpio(171);
++ omap_request_gpio(172);
++ omap_request_gpio(173);
++ omap_set_gpio_direction(171, 1);
++ omap_set_gpio_direction(172, 1);
++ omap_set_gpio_direction(173, 1);
++
++ beagle_revision = omap_get_gpio_datain(173) << 2 |
++ omap_get_gpio_datain(172) << 1 |
++ omap_get_gpio_datain(171);
++ omap_free_gpio(171);
++ omap_free_gpio(172);
++ omap_free_gpio(173);
+ }
+
+ /*
+@@ -106,9 +103,31 @@ int misc_init_r(void)
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
++ beagle_identify();
++
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
++ printf("Board revision ");
++ switch (beagle_revision) {
++ case REVISION_AXBX:
++ printf("Ax/Bx\n");
++ break;
++ case REVISION_CX:
++ printf("C1/C2/C3\n");
++ MUX_BEAGLE_C();
++ break;
++ case REVISION_C4:
++ printf("C4\n");
++ MUX_BEAGLE_C();
++ break;
++ case REVISION_D:
++ printf("D\n");
++ break;
++ default:
++ printf("unknown 0x%02x\n", beagle_revision);
++ }
++
+ /* Configure GPIOs to output */
+ writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+ writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+@@ -120,8 +139,6 @@ int misc_init_r(void)
+ writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+
+- beagle_identify();
+-
+ dieid_num_r();
+
+ return 0;
+@@ -136,8 +153,4 @@ int misc_init_r(void)
+ void set_muxconf_regs(void)
+ {
+ MUX_BEAGLE();
+-
+- if (beagle_revision_c) {
+- MUX_BEAGLE_C();
+- }
+ }
+diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
+index 7fe6275..d95fd78 100644
+--- a/board/ti/beagle/beagle.h
++++ b/board/ti/beagle/beagle.h
+@@ -34,6 +34,11 @@ const omap3_sysinfo sysinfo = {
+ };
+
+ #define BOARD_REVISION_MASK (0x1 << 11)
++/* BeagleBoard revisions */
++#define REVISION_AXBX 0x7
++#define REVISION_CX 0x6
++#define REVISION_C4 0x5
++#define REVISION_D 0x0
+
+ /*
+ * IEN - Input Enable
+@@ -264,7 +269,7 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
+- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\
++ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+--
+1.6.6.1
+
--- /dev/null
+From efc587fb24a5246f5a436a057320687a1b7847c6 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Wed, 10 Feb 2010 15:23:19 -0800
+Subject: [PATCH 04/37] OMAP3: Set VAUX2 to 1.8V for EHCI PHY on Beagle Rev C4 boards
+
+---
+ board/ti/beagle/beagle.c | 5 +++++
+ drivers/power/twl4030.c | 45 +++++++++++++++++++++++++--------------------
+ include/twl4030.h | 15 +++++++++++++++
+ 3 files changed, 45 insertions(+), 20 deletions(-)
+
+diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
+index ba16dd7..b4ea7e6 100644
+--- a/board/ti/beagle/beagle.c
++++ b/board/ti/beagle/beagle.c
+@@ -120,6 +120,11 @@ int misc_init_r(void)
+ case REVISION_C4:
+ printf("C4\n");
+ MUX_BEAGLE_C();
++ /* Set VAUX2 to 1.8V for EHCI PHY */
++ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
++ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
++ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
++ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ break;
+ case REVISION_D:
+ printf("D\n");
+diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
+index eb066cb..f354834 100644
+--- a/drivers/power/twl4030.c
++++ b/drivers/power/twl4030.c
+@@ -59,57 +59,62 @@ void twl4030_power_reset_init(void)
+ }
+ }
+
+-
+-/*
+- * Power Init
+- */
+-#define DEV_GRP_P1 0x20
+-#define VAUX3_VSEL_28 0x03
+-#define DEV_GRP_ALL 0xE0
+-#define VPLL2_VSEL_18 0x05
+-#define VDAC_VSEL_18 0x03
+-
+ void twl4030_power_init(void)
+ {
+ unsigned char byte;
+
+ /* set VAUX3 to 2.8V */
+- byte = DEV_GRP_P1;
++ byte = TWL4030_PM_RECEIVER_DEV_GRP_P1;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VAUX3_DEV_GRP);
+- byte = VAUX3_VSEL_28;
++ byte = TWL4030_PM_RECEIVER_VAUX3_VSEL_28;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VAUX3_DEDICATED);
+
+ /* set VPLL2 to 1.8V */
+- byte = DEV_GRP_ALL;
++ byte = TWL4030_PM_RECEIVER_DEV_GRP_ALL;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VPLL2_DEV_GRP);
+- byte = VPLL2_VSEL_18;
++ byte = TWL4030_PM_RECEIVER_VPLL2_VSEL_18;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VPLL2_DEDICATED);
+
+ /* set VDAC to 1.8V */
+- byte = DEV_GRP_P1;
++ byte = TWL4030_PM_RECEIVER_DEV_GRP_P1;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VDAC_DEV_GRP);
+- byte = VDAC_VSEL_18;
++ byte = TWL4030_PM_RECEIVER_VDAC_VSEL_18;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VDAC_DEDICATED);
+ }
+
+-#define VMMC1_VSEL_30 0x02
+-
+ void twl4030_power_mmc_init(void)
+ {
+ unsigned char byte;
+
+- byte = DEV_GRP_P1;
++ byte = TWL4030_PM_RECEIVER_DEV_GRP_P1;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VMMC1_DEV_GRP);
+
+ /* 3 Volts */
+- byte = VMMC1_VSEL_30;
++ byte = TWL4030_PM_RECEIVER_VMMC1_VSEL_30;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VMMC1_DEDICATED);
+ }
++
++/*
++ * Generic function to select Device Group and Voltage
++ */
++void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
++ u8 dev_grp, u8 dev_grp_sel)
++{
++ /* Select the Device Group */
++ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
++ dev_grp);
++
++ /* Select the Voltage */
++ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
++ vsel_reg);
++}
++
++
+diff --git a/include/twl4030.h b/include/twl4030.h
+index 2b2f5ae..cc99403 100644
+--- a/include/twl4030.h
++++ b/include/twl4030.h
+@@ -471,6 +471,21 @@
+ #define TWL4030_USB_PHY_CLK_CTRL_STS 0xFF
+
+ /*
++ * Voltage Selection in PM Receiver Module
++ */
++#define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05
++#define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03
++#define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05
++#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03
++#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02
++
++/*
++ * Device Selection in PM Receiver Module
++ */
++#define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20
++#define TWL4030_PM_RECEIVER_DEV_GRP_ALL 0xE0
++
++/*
+ * Convience functions to read and write from TWL4030
+ *
+ * chip_no is the i2c address, it must be one of the chip addresses
+--
+1.6.6.1
+
--- /dev/null
+From 27072274450ea8de1994744782397452b99814cc Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Wed, 3 Feb 2010 12:26:30 -0800
+Subject: [PATCH 05/37] OMAP3: add entry for rev 3.1.2, check and display max cpu clock for rev > 3.0
+
+---
+ cpu/arm_cortexa8/omap3/sys_info.c | 24 ++++++++++++++++++++++--
+ include/asm-arm/arch-omap3/cpu.h | 8 +++++++-
+ include/asm-arm/arch-omap3/omap3.h | 3 ++-
+ 3 files changed, 31 insertions(+), 4 deletions(-)
+
+diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
+index 08fb32e..e227f67 100644
+--- a/cpu/arm_cortexa8/omap3/sys_info.c
++++ b/cpu/arm_cortexa8/omap3/sys_info.c
+@@ -39,7 +39,10 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
+ "2.0",
+ "2.1",
+ "3.0",
+- "3.1"};
++ "3.1",
++ "UNKNOWN",
++ "UNKNOWN",
++ "3.1.2"};
+
+ /*****************************************************************
+ * dieid_num_r(void) - read and set die ID
+@@ -104,6 +107,16 @@ u32 get_cpu_rev(void)
+ }
+ }
+
++/*****************************************************************
++ * get_sku_id(void) - read sku_id to get info on max clock rate
++ *****************************************************************/
++u32 get_sku_id(void)
++{
++ struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
++ return (readl(&id_base->sku_id) & SKUID_CLK_MASK);
++}
++
++
+ /****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+@@ -291,9 +304,16 @@ int print_cpuinfo (void)
+ sec_s = "?";
+ }
+
+- printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n",
++ printf("OMAP%s-%s ES%s, CPU-OPP2, L3-165MHz, ",
+ cpu_s, sec_s, rev_s[get_cpu_rev()]);
+
++ printf("Max clock-");
++ if ((get_cpu_rev() >= CPU_3XX_ES31) && (get_sku_id() == SKUID_CLK_720MHZ))
++ printf("720Mhz\n");
++ else printf("600Mhz\n");
++
++
++
+ return 0;
+ }
+ #endif /* CONFIG_DISPLAY_CPUINFO */
+diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
+index aa8de32..f769571 100644
+--- a/include/asm-arm/arch-omap3/cpu.h
++++ b/include/asm-arm/arch-omap3/cpu.h
+@@ -72,7 +72,8 @@ struct ctrl_id {
+ u8 res1[0x4];
+ u32 idcode; /* 0x04 */
+ u32 prod_id; /* 0x08 */
+- u8 res2[0x0C];
++ u32 sku_id; /* 0x0c */
++ u8 res2[0x08];
+ u32 die_id_0; /* 0x18 */
+ u32 die_id_1; /* 0x1C */
+ u32 die_id_2; /* 0x20 */
+@@ -89,6 +90,11 @@ struct ctrl_id {
+ #define HS_DEVICE 0x2
+ #define GP_DEVICE 0x3
+
++/* device speed */
++#define SKUID_CLK_MASK 0xf
++#define SKUID_CLK_600MHZ 0x0
++#define SKUID_CLK_720MHZ 0x8
++
+ #define GPMC_BASE (OMAP34XX_GPMC_BASE)
+ #define GPMC_CONFIG_CS0 0x60
+ #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
+diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
+index 12815f6..1349b8b 100644
+--- a/include/asm-arm/arch-omap3/omap3.h
++++ b/include/asm-arm/arch-omap3/omap3.h
+@@ -176,7 +176,8 @@ struct gpio {
+ #define CPU_3XX_ES21 2
+ #define CPU_3XX_ES30 3
+ #define CPU_3XX_ES31 4
+-#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1)
++#define CPU_3XX_ES312 7
++#define CPU_3XX_MAX_REV 8
+
+ #define CPU_3XX_ID_SHIFT 28
+
+--
+1.6.6.1
+
--- /dev/null
+From 1b082bb4a8ba5b7bee727baf3cd048e1785c8abd Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Wed, 3 Feb 2010 14:39:14 -0800
+Subject: [PATCH 06/37] OMAP3: add mpurate boot arg for overo and beagle
+
+allows one to set the omap clock rate via "setenv mpurate 720" for example
+---
+ include/configs/omap3_beagle.h | 3 +++
+ include/configs/omap3_overo.h | 3 +++
+ 2 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
+index 87e3dd0..ce347cd 100644
+--- a/include/configs/omap3_beagle.h
++++ b/include/configs/omap3_beagle.h
+@@ -182,6 +182,7 @@
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyS2,115200n8\0" \
++ "mpurate=500\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+@@ -190,6 +191,7 @@
+ "nandroot=/dev/mtdblock4 rw\0" \
+ "nandrootfstype=jffs2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
++ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+@@ -197,6 +199,7 @@
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
++ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
+index 0d24758..295cce6 100644
+--- a/include/configs/omap3_overo.h
++++ b/include/configs/omap3_overo.h
+@@ -152,6 +152,7 @@
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
++ "mpurate=500\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+@@ -160,6 +161,7 @@
+ "nandroot=/dev/mtdblock4 rw\0" \
+ "nandrootfstype=jffs2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
++ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+@@ -167,6 +169,7 @@
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
++ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+--
+1.6.6.1
+
--- /dev/null
+From 129dccd106ea5862f3ff25c368102bf656472f7f Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Fri, 12 Feb 2010 12:17:48 -0800
+Subject: [PATCH 07/37] OMAP3: detect expansion board type/version using eeprom contents
+
+---
+ board/overo/overo.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 92 insertions(+), 0 deletions(-)
+
+diff --git a/board/overo/overo.c b/board/overo/overo.c
+index 3df1a12..2838a1f 100644
+--- a/board/overo/overo.c
++++ b/board/overo/overo.c
+@@ -39,6 +39,31 @@
+ #include <asm/mach-types.h>
+ #include "overo.h"
+
++static struct {
++ unsigned int device_vendor;
++ unsigned char revision;
++ unsigned char content;
++ unsigned char data[6];
++} expansion_config;
++
++#define TWL4030_I2C_BUS 0
++
++#define EXPANSION_EEPROM_I2C_BUS 2
++#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
++
++#define GUMSTIX_VENDORID 0x0200
++
++#define GUMSTIX_SUMMIT 0x01000200
++#define GUMSTIX_TOBI 0x02000200
++#define GUMSTIX_TOBI_DUO 0x03000200
++#define GUMSTIX_PALO35 0x04000200
++#define GUMSTIX_PALO43 0x05000200
++#define GUMSTIX_CHESTNUT43 0x06000200
++#define GUMSTIX_PINTO 0x07000200
++
++#define GUMSTIX_NO_EEPROM 0xfffffffe
++#define GUMSTIX_UNKNOWN 0xffffffff
++
+ #if defined(CONFIG_CMD_NET)
+ static void setup_net_chip(void);
+ #endif
+@@ -130,6 +155,31 @@ int get_board_revision(void) {
+ }
+
+ /*
++ * Routine: get_expansion_id
++ * Description: This function checks for expansion board by checking I2C
++ * bus 2 for the availability of an AT24C01B serial EEPROM.
++ * returns the device_vendor field from the EEPROM
++ */
++unsigned int get_expansion_id(void)
++{
++ i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
++
++ /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
++ if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1)
++ return GUMSTIX_NO_EEPROM;
++
++ /* read configuration data */
++ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
++ sizeof(expansion_config));
++
++ if ( (expansion_config.device_vendor & 0xffff) != GUMSTIX_VENDORID )
++ return GUMSTIX_UNKNOWN;
++ else
++ return expansion_config.device_vendor;
++}
++
++
++/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+@@ -156,6 +206,48 @@ int misc_init_r(void)
+ printf(" unsupported\n");
+ }
+
++ switch (get_expansion_id()) {
++ case GUMSTIX_SUMMIT:
++ printf("Recognized Summit expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.data);
++ setenv("defaultdisplay", "dvi");
++ break;
++ case GUMSTIX_TOBI:
++ printf("Recognized Tobi expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.data);
++ setenv("defaultdisplay", "dvi");
++ break;
++ case GUMSTIX_TOBI_DUO:
++ printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.data);
++ break;
++ case GUMSTIX_PALO35:
++ printf("Recognized Palo 35 expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.data);
++ setenv("defaultdisplay", "lcd35");
++ break;
++ case GUMSTIX_PALO43:
++ printf("Recognized Palo 43 expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.data);
++ setenv("defaultdisplay", "lcd43");
++ break;
++ case GUMSTIX_CHESTNUT43:
++ printf("Recognized Chestnut 43 expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.data);
++ setenv("defaultdisplay", "lcd43");
++ break;
++ case GUMSTIX_PINTO:
++ printf("Recognized Pinto expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.data);
++ break;
++ case GUMSTIX_NO_EEPROM:
++ printf("No EEPROM on expansion board\n");
++ break;
++ case GUMSTIX_UNKNOWN:
++ printf("Unrecognized expansion board\n");
++ }
++
++ i2c_set_bus_num(TWL4030_I2C_BUS);
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+--
+1.6.6.1
+
--- /dev/null
+From 4fb2bbcae8f283c46e762aa93b25cbbd55bab8b6 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 16 Feb 2010 09:58:01 -0800
+Subject: [PATCH 08/37] OMAP3: Overo: enable config eeprom to set u-boot env variable
+
+---
+ board/overo/overo.c | 21 +++++++++++++--------
+ 1 files changed, 13 insertions(+), 8 deletions(-)
+
+diff --git a/board/overo/overo.c b/board/overo/overo.c
+index 2838a1f..f6093d2 100644
+--- a/board/overo/overo.c
++++ b/board/overo/overo.c
+@@ -43,7 +43,9 @@ static struct {
+ unsigned int device_vendor;
+ unsigned char revision;
+ unsigned char content;
+- unsigned char data[6];
++ unsigned char fab_revision[8];
++ unsigned char env_var[16];
++ unsigned char env_setting[64];
+ } expansion_config;
+
+ #define TWL4030_I2C_BUS 0
+@@ -209,36 +211,36 @@ int misc_init_r(void)
+ switch (get_expansion_id()) {
+ case GUMSTIX_SUMMIT:
+ printf("Recognized Summit expansion board (rev %d %s)\n",
+- expansion_config.revision, expansion_config.data);
++ expansion_config.revision, expansion_config.fab_revision);
+ setenv("defaultdisplay", "dvi");
+ break;
+ case GUMSTIX_TOBI:
+ printf("Recognized Tobi expansion board (rev %d %s)\n",
+- expansion_config.revision, expansion_config.data);
++ expansion_config.revision, expansion_config.fab_revision);
+ setenv("defaultdisplay", "dvi");
+ break;
+ case GUMSTIX_TOBI_DUO:
+ printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
+- expansion_config.revision, expansion_config.data);
++ expansion_config.revision, expansion_config.fab_revision);
+ break;
+ case GUMSTIX_PALO35:
+ printf("Recognized Palo 35 expansion board (rev %d %s)\n",
+- expansion_config.revision, expansion_config.data);
++ expansion_config.revision, expansion_config.fab_revision);
+ setenv("defaultdisplay", "lcd35");
+ break;
+ case GUMSTIX_PALO43:
+ printf("Recognized Palo 43 expansion board (rev %d %s)\n",
+- expansion_config.revision, expansion_config.data);
++ expansion_config.revision, expansion_config.fab_revision);
+ setenv("defaultdisplay", "lcd43");
+ break;
+ case GUMSTIX_CHESTNUT43:
+ printf("Recognized Chestnut 43 expansion board (rev %d %s)\n",
+- expansion_config.revision, expansion_config.data);
++ expansion_config.revision, expansion_config.fab_revision);
+ setenv("defaultdisplay", "lcd43");
+ break;
+ case GUMSTIX_PINTO:
+ printf("Recognized Pinto expansion board (rev %d %s)\n",
+- expansion_config.revision, expansion_config.data);
++ expansion_config.revision, expansion_config.fab_revision);
+ break;
+ case GUMSTIX_NO_EEPROM:
+ printf("No EEPROM on expansion board\n");
+@@ -247,6 +249,9 @@ int misc_init_r(void)
+ printf("Unrecognized expansion board\n");
+ }
+
++ if (expansion_config.content == 1)
++ setenv(expansion_config.env_var, expansion_config.env_setting);
++
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+--
+1.6.6.1
+
--- /dev/null
+From 0ddd7f44f04b47d16d33a6b232b288ebdb1c9992 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 16 Feb 2010 10:00:45 -0800
+Subject: [PATCH 09/37] OMAP3: Overo: enable input on MMC1_CLK and MMC3_CLK pinmux
+
+---
+ board/overo/overo.h | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/board/overo/overo.h b/board/overo/overo.h
+index e120e09..ff936dd 100644
+--- a/board/overo/overo.h
++++ b/board/overo/overo.h
+@@ -200,7 +200,7 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
++ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+@@ -301,7 +301,7 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\
++ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\
+--
+1.6.6.1
+
--- /dev/null
+From 405a5a151c8d42f157dc48731f6e607675156774 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 16 Feb 2010 10:03:14 -0800
+Subject: [PATCH 10/37] OMAP3: Overo: set CONFIG_SYS_I2C_SPEED to 400Khz
+
+---
+ include/configs/omap3_overo.h | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
+index 295cce6..fdbeb67 100644
+--- a/include/configs/omap3_overo.h
++++ b/include/configs/omap3_overo.h
+@@ -112,7 +112,7 @@
+
+ #define CONFIG_SYS_NO_FLASH
+ #define CONFIG_HARD_I2C 1
+-#define CONFIG_SYS_I2C_SPEED 100000
++#define CONFIG_SYS_I2C_SPEED 400000
+ #define CONFIG_SYS_I2C_SLAVE 1
+ #define CONFIG_SYS_I2C_BUS 0
+ #define CONFIG_SYS_I2C_BUS_SELECT 1
+--
+1.6.6.1
+
--- /dev/null
+From 991f54c9da846ab9571c256adf42d8d80d044bdc Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 16 Feb 2010 10:04:30 -0800
+Subject: [PATCH 11/37] OMAP3: trim excessively long delays in i2c driver
+
+---
+ drivers/i2c/omap24xx_i2c.c | 8 ++++----
+ 1 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
+index 30a8b4c..ba47fc4 100644
+--- a/drivers/i2c/omap24xx_i2c.c
++++ b/drivers/i2c/omap24xx_i2c.c
+@@ -148,7 +148,7 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+ if (status & I2C_STAT_XRDY) {
+ /* Important: have to use byte access */
+ writeb (regoffset, &i2c_base->data);
+- udelay (20000);
++ udelay (2000);
+ if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
+ i2c_error = 1;
+ }
+@@ -160,7 +160,7 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+ /* free bus, otherwise we can't use a combined transction */
+ writew (0, &i2c_base->con);
+ while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) {
+- udelay (10000);
++ udelay (1000);
+ /* Have to clear pending interrupt to clear I2C_STAT */
+ writew (0xFFFF, &i2c_base->stat);
+ }
+@@ -181,7 +181,7 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+ #else
+ *value = readw (&i2c_base->data);
+ #endif
+- udelay (20000);
++ udelay (2000);
+ } else {
+ i2c_error = 1;
+ }
+@@ -190,7 +190,7 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+ writew (I2C_CON_EN, &i2c_base->con);
+ while (readw (&i2c_base->stat)
+ || (readw (&i2c_base->con) & I2C_CON_MST)) {
+- udelay (10000);
++ udelay (1000);
+ writew (0xFFFF, &i2c_base->stat);
+ }
+ }
+--
+1.6.6.1
+
--- /dev/null
+From ad1a2c047554deae2e1608d025c4f6891cf8f116 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Fri, 26 Feb 2010 12:40:26 -0800
+Subject: [PATCH 12/37] OMAP3: Overo: allow expansion boards with any vendor ID
+
+---
+ board/overo/overo.c | 10 +++-------
+ 1 files changed, 3 insertions(+), 7 deletions(-)
+
+diff --git a/board/overo/overo.c b/board/overo/overo.c
+index f6093d2..ec186ec 100644
+--- a/board/overo/overo.c
++++ b/board/overo/overo.c
+@@ -63,8 +63,7 @@ static struct {
+ #define GUMSTIX_CHESTNUT43 0x06000200
+ #define GUMSTIX_PINTO 0x07000200
+
+-#define GUMSTIX_NO_EEPROM 0xfffffffe
+-#define GUMSTIX_UNKNOWN 0xffffffff
++#define GUMSTIX_NO_EEPROM 0xffffffff
+
+ #if defined(CONFIG_CMD_NET)
+ static void setup_net_chip(void);
+@@ -174,10 +173,7 @@ unsigned int get_expansion_id(void)
+ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
+ sizeof(expansion_config));
+
+- if ( (expansion_config.device_vendor & 0xffff) != GUMSTIX_VENDORID )
+- return GUMSTIX_UNKNOWN;
+- else
+- return expansion_config.device_vendor;
++ return expansion_config.device_vendor;
+ }
+
+
+@@ -245,7 +241,7 @@ int misc_init_r(void)
+ case GUMSTIX_NO_EEPROM:
+ printf("No EEPROM on expansion board\n");
+ break;
+- case GUMSTIX_UNKNOWN:
++ default:
+ printf("Unrecognized expansion board\n");
+ }
+
+--
+1.6.6.1
+
--- /dev/null
+From 305e2cb16f4f6e8c7f13120e6a98bb1e999c764f Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Fri, 26 Feb 2010 12:42:30 -0800
+Subject: [PATCH 13/37] OMAP3: Overo: change address of expansion eeprom to 0x51 so as to not conflict with EDID address
+
+---
+ board/overo/overo.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/board/overo/overo.c b/board/overo/overo.c
+index ec186ec..f96e7ff 100644
+--- a/board/overo/overo.c
++++ b/board/overo/overo.c
+@@ -51,7 +51,7 @@ static struct {
+ #define TWL4030_I2C_BUS 0
+
+ #define EXPANSION_EEPROM_I2C_BUS 2
+-#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
++#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
+
+ #define GUMSTIX_VENDORID 0x0200
+
+--
+1.6.6.1
+
--- /dev/null
+From 63de99ce613bbfce792ee46d14b324273e6a0d29 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 23 Mar 2010 09:04:50 -0700
+Subject: [PATCH 14/37] OMAP3: board.c: don't attempt to set up second RAM bank, assume x-load has already done this
+
+---
+ cpu/arm_cortexa8/omap3/board.c | 19 +++++++++----------
+ 1 files changed, 9 insertions(+), 10 deletions(-)
+
+diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
+index 7b78fa4..0126152 100644
+--- a/cpu/arm_cortexa8/omap3/board.c
++++ b/cpu/arm_cortexa8/omap3/board.c
+@@ -232,6 +232,7 @@ void s_init(void)
+
+ per_clocks_enable();
+
++ /* FIXME: u-boot's sdrc setup is broken */
+ if (!in_sdram)
+ sdrc_init();
+ }
+@@ -281,16 +282,14 @@ int dram_init(void)
+ {
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned int size0 = 0, size1 = 0;
+-
+- /*
+- * If a second bank of DDR is attached to CS1 this is
+- * where it can be started. Early init code will init
+- * memory on CS0.
+- */
+- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+- do_sdrc_init(CS1, NOT_EARLY);
+- make_cs1_contiguous();
+- }
++ struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
++ struct sdrc_actim *sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
++
++ /* x-load sets up the second bank but */
++ /* doesn't test to see if it is there */
++ /* do so now, disable if not present */
++ if (!mem_ok(CS1))
++ writel(0, &sdrc_base->cs[1].mcfg);
+
+ size0 = get_sdr_cs_size(CS0);
+ size1 = get_sdr_cs_size(CS1);
+--
+1.6.6.1
+
--- /dev/null
+From f2e3d22fb1963d08844edee45f7d7d6beba32152 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 23 Mar 2010 09:06:49 -0700
+Subject: [PATCH 15/37] OMAP3: mem.c: enhance the RAM test
+
+---
+ cpu/arm_cortexa8/omap3/mem.c | 28 +++++++++++++++-------------
+ 1 files changed, 15 insertions(+), 13 deletions(-)
+
+diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
+index dfb7e4c..b828097 100644
+--- a/cpu/arm_cortexa8/omap3/mem.c
++++ b/cpu/arm_cortexa8/omap3/mem.c
+@@ -106,21 +106,23 @@ void make_cs1_contiguous(void)
+ *******************************************************/
+ u32 mem_ok(u32 cs)
+ {
+- u32 val1, val2, addr;
++ u32 i, val1, val2, addr, size;
+ u32 pattern = 0x12345678;
+
+- addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
+-
+- writel(0x0, addr + 0x400); /* clear pos A */
+- writel(pattern, addr); /* pattern to pos B */
+- writel(0x0, addr + 4); /* remove pattern off the bus */
+- val1 = readl(addr + 0x400); /* get pos A value */
+- val2 = readl(addr); /* get val2 */
++ size = get_sdr_cs_offset(cs);
++ addr = OMAP34XX_SDRC_CS0 + size;
++
++ for (i = 0; i < size; i+=1024) {
++ writel(pattern - i, addr + i);
++ }
+
+- if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
+- return 0;
+- else
+- return 1;
++ for (i = 0; i < size; i+=1024) {
++ val1 = readl(addr + i);
++ if (val1 != (pattern - i)) {
++ return 0;
++ }
++ }
++ return 1;
+ }
+
+ /********************************************************
+--
+1.6.6.1
+
--- /dev/null
+From 794e4aa6a5aa5fbe71b08bfe8f5f5f65078fbc68 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 23 Mar 2010 09:12:16 -0700
+Subject: [PATCH 16/37] env_nand.c: fail gracefully if no nand is present
+
+---
+ common/env_nand.c | 4 ++++
+ 1 files changed, 4 insertions(+), 0 deletions(-)
+
+diff --git a/common/env_nand.c b/common/env_nand.c
+index a15a950..325f112 100644
+--- a/common/env_nand.c
++++ b/common/env_nand.c
+@@ -268,6 +268,10 @@ int readenv (size_t offset, u_char * buf)
+
+ u_char *char_ptr;
+
++ /* fail if no nand detected */
++ if (nand_info[0].type == 0)
++ return 1;
++
+ blocksize = nand_info[0].erasesize;
+ len = min(blocksize, CONFIG_ENV_SIZE);
+
+--
+1.6.6.1
+
--- /dev/null
+From 34622e1e89b615c999480ab48ec004c16f8ca2d5 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 23 Mar 2010 09:15:29 -0700
+Subject: [PATCH 17/37] OMAP3: add definitions to support sysinfo cpu and cpu family detection
+
+---
+ include/asm-arm/arch-omap3/cpu.h | 6 ------
+ include/asm-arm/arch-omap3/omap3.h | 29 +++++++++++++++++++++++++++++
+ 2 files changed, 29 insertions(+), 6 deletions(-)
+
+diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
+index f769571..d9eec7e 100644
+--- a/include/asm-arm/arch-omap3/cpu.h
++++ b/include/asm-arm/arch-omap3/cpu.h
+@@ -60,12 +60,6 @@ struct ctrl {
+ #endif /* __ASSEMBLY__ */
+ #endif /* __KERNEL_STRICT_NAMES */
+
+-/* cpu type */
+-#define OMAP3503 0x5c00
+-#define OMAP3515 0x1c00
+-#define OMAP3525 0x4c00
+-#define OMAP3530 0x0c00
+-
+ #ifndef __KERNEL_STRICT_NAMES
+ #ifndef __ASSEMBLY__
+ struct ctrl_id {
+diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
+index 1349b8b..3957c79 100644
+--- a/include/asm-arm/arch-omap3/omap3.h
++++ b/include/asm-arm/arch-omap3/omap3.h
+@@ -184,4 +184,33 @@ struct gpio {
+ #define WIDTH_8BIT 0x0000
+ #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
+
++/*
++ * Hawkeye values
++ */
++#define HAWKEYE_OMAP34XX 0xb7ae
++#define HAWKEYE_AM35XX 0xb868
++#define HAWKEYE_OMAP36XX 0xb891
++
++#define HAWKEYE_SHIFT 12
++
++/*
++ * Define CPU families
++ */
++#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
++#define CPU_AM35XX 0x3500 /* AM35xx devices */
++#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
++
++/*
++ * Control status register values corresponding to cpu variants
++ */
++#define OMAP3503 0x5c00
++#define OMAP3515 0x1c00
++#define OMAP3525 0x4c00
++#define OMAP3530 0x0c00
++
++#define AM3505 0x5c00
++#define AM3517 0x1c00
++
++#define OMAP3730 0x0c00
++
+ #endif
+--
+1.6.6.1
+
--- /dev/null
+From 8480eb0272865078290146031e09eb70baed3f6e Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 23 Mar 2010 09:17:59 -0700
+Subject: [PATCH 18/37] OMAP3 sys_info: update cpu detection for 36XX/37XX
+
+---
+ cpu/arm_cortexa8/omap3/sys_info.c | 137 ++++++++++++++++++++++++++++---------
+ 1 files changed, 105 insertions(+), 32 deletions(-)
+
+diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
+index e227f67..e32a846 100644
+--- a/cpu/arm_cortexa8/omap3/sys_info.c
++++ b/cpu/arm_cortexa8/omap3/sys_info.c
+@@ -79,32 +79,72 @@ u32 get_cpu_type(void)
+ }
+
+ /******************************************
+- * get_cpu_rev(void) - extract version info
++ * get_cpu_id(void) - extract cpu id
++ * returns 0 for ES1.0, cpuid otherwise
+ ******************************************/
+-u32 get_cpu_rev(void)
++u32 get_cpu_id(void)
+ {
+- u32 cpuid = 0;
+ struct ctrl_id *id_base;
++ u32 cpuid = 0;
+
+ /*
+ * On ES1.0 the IDCODE register is not exposed on L4
+ * so using CPU ID to differentiate between ES1.0 and > ES1.0.
+ */
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
+- if ((cpuid & 0xf) == 0x0)
+- return CPU_3XX_ES10;
+- else {
++ if ((cpuid & 0xf) == 0x0) {
++ return 0;
++ } else {
+ /* Decode the IDs on > ES1.0 */
+ id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
+
+- cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
++ cpuid = readl(&id_base->idcode);
++ }
+
+- /* Some early ES2.0 seem to report ID 0, fix this */
+- if(cpuid == 0)
+- cpuid = CPU_3XX_ES20;
++ return cpuid;
++}
+
+- return cpuid;
++/******************************************
++ * get_cpu_family(void) - extract cpu info
++ ******************************************/
++u32 get_cpu_family(void)
++{
++ u16 hawkeye;
++ u32 cpu_family;
++ u32 cpuid = get_cpu_id();
++
++ if (cpuid == 0)
++ return CPU_OMAP34XX;
++
++ hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
++ switch(hawkeye) {
++ case HAWKEYE_OMAP34XX:
++ cpu_family = CPU_OMAP34XX;
++ break;
++ case HAWKEYE_AM35XX:
++ cpu_family = CPU_AM35XX;
++ break;
++ case HAWKEYE_OMAP36XX:
++ cpu_family = CPU_OMAP36XX;
++ break;
++ default:
++ cpu_family = CPU_OMAP34XX;
+ }
++
++ return cpu_family;
++}
++
++/******************************************
++ * get_cpu_rev(void) - extract version info
++ ******************************************/
++u32 get_cpu_rev(void)
++{
++ u32 cpuid = get_cpu_id();
++
++ if (cpuid == 0)
++ return CPU_3XX_ES10;
++ else
++ return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
+ }
+
+ /*****************************************************************
+@@ -267,24 +307,57 @@ u32 get_device_type(void)
+ */
+ int print_cpuinfo (void)
+ {
+- char *cpu_s, *sec_s;
+-
+- switch (get_cpu_type()) {
+- case OMAP3503:
+- cpu_s = "3503";
+- break;
+- case OMAP3515:
+- cpu_s = "3515";
++ char *cpu_family_s, *cpu_s, *sec_s;
++
++ switch(get_cpu_family()) {
++ case CPU_OMAP34XX:
++ cpu_family_s = "OMAP";
++ switch (get_cpu_type()) {
++ case OMAP3503:
++ cpu_s = "3503";
++ break;
++ case OMAP3515:
++ cpu_s = "3515";
++ break;
++ case OMAP3525:
++ cpu_s = "3525";
++ break;
++ case OMAP3530:
++ cpu_s = "3530";
++ break;
++ default:
++ cpu_s = "35XX";
++ break;
++ }
+ break;
+- case OMAP3525:
+- cpu_s = "3525";
++ case CPU_AM35XX:
++ cpu_family_s = "AM";
++ switch (get_cpu_type()) {
++ case AM3505:
++ cpu_s = "3505";
++ break;
++ case AM3517:
++ cpu_s = "3517";
++ break;
++ default:
++ cpu_s = "35XX";
++ break;
++ }
+ break;
+- case OMAP3530:
+- cpu_s = "3530";
++ case CPU_OMAP36XX:
++ cpu_family_s = "OMAP";
++ switch (get_cpu_type()) {
++ case OMAP3730:
++ cpu_s = "3630/3730";
++ break;
++ default:
++ cpu_s = "36XX/37XX";
++ break;
++ }
+ break;
+ default:
++ cpu_family_s = "OMAP";
+ cpu_s = "35XX";
+- break;
+ }
+
+ switch (get_device_type()) {
+@@ -304,16 +377,16 @@ int print_cpuinfo (void)
+ sec_s = "?";
+ }
+
+- printf("OMAP%s-%s ES%s, CPU-OPP2, L3-165MHz, ",
+- cpu_s, sec_s, rev_s[get_cpu_rev()]);
++ printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, ",
++ cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]);
+
+- printf("Max clock-");
+- if ((get_cpu_rev() >= CPU_3XX_ES31) && (get_sku_id() == SKUID_CLK_720MHZ))
+- printf("720Mhz\n");
+- else printf("600Mhz\n");
++ if (get_cpu_family() == CPU_OMAP34XX)
++ if ((get_cpu_rev() >= CPU_3XX_ES31) &&
++ (get_sku_id() == SKUID_CLK_720MHZ))
++ printf("Max clock-720Mhz\n");
++ else printf("Max clock-600Mhz\n");
++ else printf("\n");
+
+-
+-
+ return 0;
+ }
+ #endif /* CONFIG_DISPLAY_CPUINFO */
+--
+1.6.6.1
+
--- /dev/null
+From 0bf419a0faa8c9dc73d7a84f93d7fcb89be3ea21 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 23 Mar 2010 09:20:56 -0700
+Subject: [PATCH 19/37] OMAP3: clocks: update clock setup for 36XX/37XX
+
+---
+ cpu/arm_cortexa8/omap3/clock.c | 559 +++++++++++++++++++++--------
+ cpu/arm_cortexa8/omap3/lowlevel_init.S | 69 ++++
+ include/asm-arm/arch-omap3/clocks.h | 17 +
+ include/asm-arm/arch-omap3/clocks_omap3.h | 27 ++
+ 4 files changed, 525 insertions(+), 147 deletions(-)
+
+diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
+index 6330c9e..538a183 100644
+--- a/cpu/arm_cortexa8/omap3/clock.c
++++ b/cpu/arm_cortexa8/omap3/clock.c
+@@ -47,17 +47,12 @@ u32 get_osc_clk_speed(void)
+ struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
+
+ val = readl(&prm_base->clksrc_ctrl);
+-
+ if (val & SYSCLKDIV_2)
+ cdiv = 2;
+- else if (val & SYSCLKDIV_1)
+- cdiv = 1;
+ else
+- /*
+- * Should never reach here! (Assume divider as 1)
+- */
+ cdiv = 1;
+
++
+ /* enable timer2 */
+ val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
+
+@@ -67,7 +62,6 @@ u32 get_osc_clk_speed(void)
+ /* Enable I and F Clocks for GPT1 */
+ val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
+ writel(val, &prcm_base->iclken_wkup);
+-
+ val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
+ writel(val, &prcm_base->fclken_wkup);
+
+@@ -87,13 +81,10 @@ u32 get_osc_clk_speed(void)
+
+ /* wait for 40 cycles */
+ while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
++
+ cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
+ cdiff = cend - cstart; /* get elapsed ticks */
+-
+- if (cdiv == 2)
+- {
+- cdiff *= 2;
+- }
++ cdiff *= cdiv;
+
+ /* based on number of ticks assign speed */
+ if (cdiff > 19000)
+@@ -135,65 +126,25 @@ void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
+ }
+ }
+
++/*
++ * OMAP3530 specific functions
++ */
++
+ /******************************************************************************
+- * prcm_init() - inits clocks for PRCM as defined in clocks.h
+- * called from SRAM, or Flash (using temp SRAM stack).
++ * Initialize CORE DPLL for OMAP34x/35x
+ *****************************************************************************/
+-void prcm_init(void)
++static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
+ {
++ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
++ dpll_param *ptr = (dpll_param *) get_core_dpll_param();
+ void (*f_lock_pll) (u32, u32, u32, u32);
+ int xip_safe, p0, p1, p2, p3;
+- u32 osc_clk = 0, sys_clkin_sel;
+- u32 clk_index, sil_index = 0;
+- struct prm *prm_base = (struct prm *)PRM_BASE;
+- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+- dpll_param *dpll_param_p;
+-
+- f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
+- SRAM_VECT_CODE);
+
+ xip_safe = is_running_in_sram();
+
+- /*
+- * Gauge the input clock speed and find out the sys_clkin_sel
+- * value corresponding to the input clock.
+- */
+- osc_clk = get_osc_clk_speed();
+- get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
++ /* Moving to the right sysclk and ES rev base */
++ ptr = ptr + (3 * clk_index) + sil_index;
+
+- /* set input crystal speed */
+- sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
+-
+- /* If the input clock is greater than 19.2M always divide/2 */
+- if (sys_clkin_sel > 2) {
+- /* input clock divider */
+- sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
+- clk_index = sys_clkin_sel / 2;
+- } else {
+- /* input clock divider */
+- sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
+- clk_index = sys_clkin_sel;
+- }
+-
+- /*
+- * The DPLL tables are defined according to sysclk value and
+- * silicon revision. The clk_index value will be used to get
+- * the values for that input sysclk from the DPLL param table
+- * and sil_index will get the values for that SysClk for the
+- * appropriate silicon rev.
+- */
+- if (get_cpu_rev())
+- sil_index = 1;
+-
+- /* Unlock MPU DPLL (slows things down, and needed later) */
+- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
+- wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);
+-
+- /* Getting the base address of Core DPLL param table */
+- dpll_param_p = (dpll_param *) get_core_dpll_param();
+-
+- /* Moving it to the right sysclk and ES rev base */
+- dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+ if (xip_safe) {
+ /*
+ * CORE DPLL
+@@ -208,34 +159,38 @@ void prcm_init(void)
+ * work. write another value and then default value.
+ */
+
+- /* m3x2 */
+- sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2 + 1);
+- /* m3x2 */
++ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
++ sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
+ sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
+- /* Set M2 */
+- sr32(&prcm_base->clksel1_pll, 27, 2, dpll_param_p->m2);
+- /* Set M */
+- sr32(&prcm_base->clksel1_pll, 16, 11, dpll_param_p->m);
+- /* Set N */
+- sr32(&prcm_base->clksel1_pll, 8, 7, dpll_param_p->n);
+- /* 96M Src */
++
++ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
++ sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
++
++ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
++ sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
++
++ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
++ sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
++
++ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32(&prcm_base->clksel1_pll, 6, 1, 0);
+- /* ssi */
++
++ /* SSI */
+ sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
+- /* fsusb */
++ /* FSUSB */
+ sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
+- /* l4 */
++ /* L4 */
+ sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
+- /* l3 */
++ /* L3 */
+ sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
+- /* gfx */
+- sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
+- /* reset mgr */
++ /* GFX */
++ sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
++ /* RESET MGR */
+ sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
+- /* FREQSEL */
+- sr32(&prcm_base->clken_pll, 4, 4, dpll_param_p->fsel);
+- /* lock mode */
+- sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
++ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
++ sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
++ /* LOCK MODE */
++ sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
+
+ wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
+ LDELAY);
+@@ -244,102 +199,411 @@ void prcm_init(void)
+ * if running from flash, jump to small relocated code
+ * area in SRAM.
+ */
++ f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
++ SRAM_VECT_CODE);
++
+ p0 = readl(&prcm_base->clken_pll);
+ sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
+- sr32(&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */
++ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
++ sr32(&p0, 4, 4, ptr->fsel);
+
+ p1 = readl(&prcm_base->clksel1_pll);
+- sr32(&p1, 27, 2, dpll_param_p->m2); /* Set M2 */
+- sr32(&p1, 16, 11, dpll_param_p->m); /* Set M */
+- sr32(&p1, 8, 7, dpll_param_p->n); /* Set N */
+- sr32(&p1, 6, 1, 0); /* set source for 96M */
++ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
++ sr32(&p1, 27, 5, ptr->m2);
++ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
++ sr32(&p1, 16, 11, ptr->m);
++ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
++ sr32(&p1, 8, 7, ptr->n);
++ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
++ sr32(&p1, 6, 1, 0);
+
+ p2 = readl(&prcm_base->clksel_core);
+- sr32(&p2, 8, 4, CORE_SSI_DIV); /* ssi */
+- sr32(&p2, 4, 2, CORE_FUSB_DIV); /* fsusb */
+- sr32(&p2, 2, 2, CORE_L4_DIV); /* l4 */
+- sr32(&p2, 0, 2, CORE_L3_DIV); /* l3 */
++ /* SSI */
++ sr32(&p2, 8, 4, CORE_SSI_DIV);
++ /* FSUSB */
++ sr32(&p2, 4, 2, CORE_FUSB_DIV);
++ /* L4 */
++ sr32(&p2, 2, 2, CORE_L4_DIV);
++ /* L3 */
++ sr32(&p2, 0, 2, CORE_L3_DIV);
+
+ p3 = (u32)&prcm_base->idlest_ckgen;
+
+ (*f_lock_pll) (p0, p1, p2, p3);
+ }
++}
+
+- /* PER DPLL */
+- sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
+- wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
+-
+- /* Getting the base address to PER DPLL param table */
+-
+- /* Set N */
+- dpll_param_p = (dpll_param *) get_per_dpll_param();
++/******************************************************************************
++ * Initialize PER DPLL for OMAP34x/35x
++ *****************************************************************************/
++static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
++{
++ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
++ dpll_param *ptr = (dpll_param *) get_per_dpll_param();
+
+ /* Moving it to the right sysclk base */
+- dpll_param_p = dpll_param_p + clk_index;
++ ptr = ptr + clk_index;
++
++ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
++ sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
++ wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
+
+ /*
+ * Errata 1.50 Workaround for OMAP3 ES1.0 only
+ * If using default divisors, write default divisor + 1
+ * and then the actual divisor value
+ */
+- sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2 + 1); /* set M6 */
+- sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); /* set M6 */
+- sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2 + 1); /* set M5 */
+- sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); /* set M5 */
+- sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2 + 1); /* set M4 */
+- sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); /* set M4 */
+- sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2 + 1); /* set M3 */
+- sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); /* set M3 */
+- sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2 + 1); /* set M2 */
+- sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2); /* set M2 */
++ /* M6 */
++ sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
++ sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
++ /* M5 */
++ sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
++ sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
++ /* M4 */
++ sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
++ sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
++ /* M3 */
++ sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
++ sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
++ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
++ sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
++ sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
+ /* Workaround end */
+
+- sr32(&prcm_base->clksel2_pll, 8, 11, dpll_param_p->m); /* set m */
+- sr32(&prcm_base->clksel2_pll, 0, 7, dpll_param_p->n); /* set n */
+- sr32(&prcm_base->clken_pll, 20, 4, dpll_param_p->fsel); /* FREQSEL */
+- sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); /* lock mode */
++ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
++ sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
++
++ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
++ sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
++
++ /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
++ sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
++
++ /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
++ sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
+ wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
++}
+
+- /* Getting the base address to MPU DPLL param table */
+- dpll_param_p = (dpll_param *) get_mpu_dpll_param();
++static void mpu_init_34xx(u32 sil_index, u32 clk_index)
++{
++ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
++ dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
+
+- /* Moving it to the right sysclk and ES rev base */
+- dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
++ /* Moving to the right sysclk and ES rev base */
++ ptr = ptr + (3 * clk_index) + sil_index;
+
+ /* MPU DPLL (unlocked already) */
+
+- /* Set M2 */
+- sr32(&prcm_base->clksel2_pll_mpu, 0, 5, dpll_param_p->m2);
+- /* Set M */
+- sr32(&prcm_base->clksel1_pll_mpu, 8, 11, dpll_param_p->m);
+- /* Set N */
+- sr32(&prcm_base->clksel1_pll_mpu, 0, 7, dpll_param_p->n);
+- /* FREQSEL */
+- sr32(&prcm_base->clken_pll_mpu, 4, 4, dpll_param_p->fsel);
+- /* lock mode */
+- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
+- wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);
+-
+- /* Getting the base address to IVA DPLL param table */
+- dpll_param_p = (dpll_param *) get_iva_dpll_param();
+-
+- /* Moving it to the right sysclk and ES rev base */
+- dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+-
+- /* IVA DPLL (set to 12*20=240MHz) */
++ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
++ sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
++
++ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
++ sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
++
++ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
++ sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
++
++ /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
++ sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
++}
++
++static void iva_init_34xx(u32 sil_index, u32 clk_index)
++{
++ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
++ dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
++
++ /* Moving to the right sysclk and ES rev base */
++ ptr = ptr + (3 * clk_index) + sil_index;
++
++ /* IVA DPLL */
++ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
+ wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
+- /* set M2 */
+- sr32(&prcm_base->clksel2_pll_iva2, 0, 5, dpll_param_p->m2);
+- /* set M */
+- sr32(&prcm_base->clksel1_pll_iva2, 8, 11, dpll_param_p->m);
+- /* set N */
+- sr32(&prcm_base->clksel1_pll_iva2, 0, 7, dpll_param_p->n);
+- /* FREQSEL */
+- sr32(&prcm_base->clken_pll_iva2, 4, 4, dpll_param_p->fsel);
+- /* lock mode */
++
++ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
++ sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
++
++ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
++ sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
++
++ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
++ sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
++
++ /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
++ sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
++
++ /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
++
+ wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
++}
++
++/*
++ * OMAP3630 specific functions
++ */
++
++/******************************************************************************
++ * Initialize PER DPLL for OMAP36x/37x
++ *****************************************************************************/
++static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
++{
++ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
++ dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
++ void (*f_lock_pll) (u32, u32, u32, u32);
++ int xip_safe, p0, p1, p2, p3;
++
++ xip_safe = is_running_in_sram();
++
++ /* Moving it to the right sysclk base */
++ ptr += clk_index;
++
++ if (xip_safe) {
++ /* CORE DPLL */
++
++ /* Select relock bypass: CM_CLKEN_PLL[0:2] */
++ sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
++ wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
++ LDELAY);
++
++ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
++ sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
++
++ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
++ sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
++
++ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
++ sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
++
++ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
++ sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
++
++ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
++ sr32(&prcm_base->clksel1_pll, 6, 1, 0);
++
++ /* SSI */
++ sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
++ /* FSUSB */
++ sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
++ /* L4 */
++ sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
++ /* L3 */
++ sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
++ /* GFX */
++ sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
++ /* RESET MGR */
++ sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
++ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
++ sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
++ /* LOCK MODE */
++ sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
++
++ wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
++ LDELAY);
++ } else if (is_running_in_flash()) {
++ /*
++ * if running from flash, jump to small relocated code
++ * area in SRAM.
++ */
++ f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
++ SRAM_VECT_CODE);
++
++ p0 = readl(&prcm_base->clken_pll);
++ sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
++ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
++ sr32(&p0, 4, 4, ptr->fsel);
++
++ p1 = readl(&prcm_base->clksel1_pll);
++ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
++ sr32(&p1, 27, 5, ptr->m2);
++ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
++ sr32(&p1, 16, 11, ptr->m);
++ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
++ sr32(&p1, 8, 7, ptr->n);
++ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
++ sr32(&p1, 6, 1, 0);
++
++ p2 = readl(&prcm_base->clksel_core);
++ /* SSI */
++ sr32(&p2, 8, 4, CORE_SSI_DIV);
++ /* FSUSB */
++ sr32(&p2, 4, 2, CORE_FUSB_DIV);
++ /* L4 */
++ sr32(&p2, 2, 2, CORE_L4_DIV);
++ /* L3 */
++ sr32(&p2, 0, 2, CORE_L3_DIV);
++
++ p3 = (u32)&prcm_base->idlest_ckgen;
++
++ (*f_lock_pll) (p0, p1, p2, p3);
++ }
++}
++
++static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
++{
++ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
++ struct dpll_per_36x_param *ptr;
++
++ ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
++
++ /* Moving it to the right sysclk base */
++ ptr += clk_index;
++
++ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
++ sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
++ wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
++
++ /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
++ sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
++
++ /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
++ sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
++
++ /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
++ sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
++
++ /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
++ sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
++
++ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
++ sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
++
++ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
++ sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
++
++ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
++ sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
++
++ /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
++ sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
++
++ /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
++ sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
++ wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
++}
++
++static void mpu_init_36xx(u32 sil_index, u32 clk_index)
++{
++ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
++ dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
++
++ /* Moving to the right sysclk */
++ ptr += clk_index;
++
++ /* MPU DPLL (unlocked already */
++
++ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
++ sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
++
++ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
++ sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
++
++ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
++ sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
++}
++
++static void iva_init_36xx(u32 sil_index, u32 clk_index)
++{
++ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
++ dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
++
++ /* Moving to the right sysclk */
++ ptr += clk_index;
++
++ /* IVA DPLL */
++ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
++ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
++ wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
++
++ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
++ sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
++
++ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
++ sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
++
++ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
++ sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
++
++ /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
++ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
++
++ wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
++}
++
++/******************************************************************************
++ * prcm_init() - inits clocks for PRCM as defined in clocks.h
++ * called from SRAM, or Flash (using temp SRAM stack).
++ *****************************************************************************/
++void prcm_init(void)
++{
++ u32 osc_clk = 0, sys_clkin_sel;
++ u32 clk_index, sil_index = 0;
++ struct prm *prm_base = (struct prm *)PRM_BASE;
++ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
++
++ /*
++ * Gauge the input clock speed and find out the sys_clkin_sel
++ * value corresponding to the input clock.
++ */
++ osc_clk = get_osc_clk_speed();
++ get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
++
++ /* set input crystal speed */
++ sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
++
++ /* If the input clock is greater than 19.2M always divide/2 */
++ if (sys_clkin_sel > 2) {
++ /* input clock divider */
++ sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
++ clk_index = sys_clkin_sel / 2;
++ } else {
++ /* input clock divider */
++ sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
++ clk_index = sys_clkin_sel;
++ }
++
++ if (get_cpu_family() == CPU_OMAP36XX) {
++ /* Unlock MPU DPLL (slows things down, and needed later) */
++ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
++ wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
++ LDELAY);
++
++ dpll3_init_36xx(0, clk_index);
++ dpll4_init_36xx(0, clk_index);
++ iva_init_36xx(0, clk_index);
++ mpu_init_36xx(0, clk_index);
++
++ /* Lock MPU DPLL to set frequency */
++ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
++ wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
++ LDELAY);
++ } else {
++ /*
++ * The DPLL tables are defined according to sysclk value and
++ * silicon revision. The clk_index value will be used to get
++ * the values for that input sysclk from the DPLL param table
++ * and sil_index will get the values for that SysClk for the
++ * appropriate silicon rev.
++ */
++ if (((get_cpu_family() == CPU_OMAP34XX)
++ && (get_cpu_rev() >= CPU_3XX_ES20)) ||
++ (get_cpu_family() == CPU_AM35XX))
++ sil_index = 1;
++
++ /* Unlock MPU DPLL (slows things down, and needed later) */
++ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
++ wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
++ LDELAY);
++
++ dpll3_init_34xx(sil_index, clk_index);
++ dpll4_init_34xx(sil_index, clk_index);
++ iva_init_34xx(sil_index, clk_index);
++ mpu_init_34xx(sil_index, clk_index);
++
++ /* Lock MPU DPLL to set frequency */
++ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
++ wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
++ LDELAY);
++ }
+
+ /* Set up GPTimers to sys_clk source only */
+ sr32(&prcm_base->clksel_per, 0, 8, 0xff);
+@@ -414,3 +678,4 @@ void per_clocks_enable(void)
+
+ sdelay(1000);
+ }
++
+diff --git a/cpu/arm_cortexa8/omap3/lowlevel_init.S b/cpu/arm_cortexa8/omap3/lowlevel_init.S
+index 73063ec..2045e4e 100644
+--- a/cpu/arm_cortexa8/omap3/lowlevel_init.S
++++ b/cpu/arm_cortexa8/omap3/lowlevel_init.S
+@@ -359,3 +359,72 @@ per_dpll_param:
+ get_per_dpll_param:
+ adr r0, per_dpll_param
+ mov pc, lr
++
++/*
++ * Tables for 36x/37x devices
++ *
++ */
++mpu_36x_dpll_param:
++/* 12MHz */
++.word 50, 0, 0, 1
++/* 13MHz */
++.word 600, 12, 0, 1
++/* 19.2MHz */
++.word 125, 3, 0, 1
++/* 26MHz */
++.word 300, 12, 0, 1
++/* 38.4MHz */
++.word 125, 7, 0, 1
++
++iva_36x_dpll_param:
++/* 12MHz */
++.word 130, 2, 0, 1
++/* 13MHz */
++.word 40, 0, 0, 1
++/* 19.2MHz */
++.word 325, 11, 0, 1
++/* 26MHz */
++.word 20, 0, 0, 1
++/* 38.4MHz */
++.word 325, 23, 0, 1
++
++core_36x_dpll_param:
++/* 12MHz */
++.word 100, 2, 0, 1
++/* 13MHz */
++.word 400, 12, 0, 1
++/* 19.2MHz */
++.word 375, 17, 0, 1
++/* 26MHz */
++.word 200, 12, 0, 1
++/* 38.4MHz */
++.word 375, 35, 0, 1
++
++per_36x_dpll_param:
++/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
++.word 12000, 360, 4, 9, 16, 5, 4, 3, 1
++.word 13000, 1728, 12, 9, 32, 18, 8, 6, 2
++.word 19200, 360, 7, 9, 16, 5, 4, 3, 1
++.word 26000, 1728, 12, 9, 32, 18, 8, 6, 2
++.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
++
++.globl get_36x_mpu_dpll_param
++get_36x_mpu_dpll_param:
++ adr r0, mpu_36x_dpll_param
++ mov pc, lr
++
++.globl get_36x_iva_dpll_param
++get_36x_iva_dpll_param:
++ adr r0, iva_36x_dpll_param
++ mov pc, lr
++
++.globl get_36x_core_dpll_param
++get_36x_core_dpll_param:
++ adr r0, core_36x_dpll_param
++ mov pc, lr
++
++.globl get_36x_per_dpll_param
++get_36x_per_dpll_param:
++ adr r0, per_36x_dpll_param
++ mov pc, lr
++
+diff --git a/include/asm-arm/arch-omap3/clocks.h b/include/asm-arm/arch-omap3/clocks.h
+index 71a0cb6..a5f2d08 100644
+--- a/include/asm-arm/arch-omap3/clocks.h
++++ b/include/asm-arm/arch-omap3/clocks.h
+@@ -51,12 +51,29 @@ typedef struct {
+ unsigned int m2;
+ } dpll_param;
+
++struct dpll_per_36x_param {
++ unsigned int sys_clk;
++ unsigned int m;
++ unsigned int n;
++ unsigned int m2;
++ unsigned int m3;
++ unsigned int m4;
++ unsigned int m5;
++ unsigned int m6;
++ unsigned int m2div;
++};
++
+ /* Following functions are exported from lowlevel_init.S */
+ extern dpll_param *get_mpu_dpll_param(void);
+ extern dpll_param *get_iva_dpll_param(void);
+ extern dpll_param *get_core_dpll_param(void);
+ extern dpll_param *get_per_dpll_param(void);
+
++extern dpll_param *get_36x_mpu_dpll_param(void);
++extern dpll_param *get_36x_iva_dpll_param(void);
++extern dpll_param *get_36x_core_dpll_param(void);
++extern dpll_param *get_36x_per_dpll_param(void);
++
+ extern void *_end_vect, *_start;
+
+ #endif
+diff --git a/include/asm-arm/arch-omap3/clocks_omap3.h b/include/asm-arm/arch-omap3/clocks_omap3.h
+index 661407b..30ef690 100644
+--- a/include/asm-arm/arch-omap3/clocks_omap3.h
++++ b/include/asm-arm/arch-omap3/clocks_omap3.h
+@@ -282,4 +282,31 @@
+ #define PER_FSEL_38P4 0x07
+ #define PER_M2_38P4 0x09
+
++/* 36XX PER DPLL */
++
++#define PER_36XX_M_12 0x1B0
++#define PER_36XX_N_12 0x05
++#define PER_36XX_FSEL_12 0x07
++#define PER_36XX_M2_12 0x09
++
++#define PER_36XX_M_13 0x360
++#define PER_36XX_N_13 0x0C
++#define PER_36XX_FSEL_13 0x03
++#define PER_36XX_M2_13 0x09
++
++#define PER_36XX_M_19P2 0x1C2
++#define PER_36XX_N_19P2 0x09
++#define PER_36XX_FSEL_19P2 0x07
++#define PER_36XX_M2_19P2 0x09
++
++#define PER_36XX_M_26 0x1B0
++#define PER_36XX_N_26 0x0C
++#define PER_36XX_FSEL_26 0x07
++#define PER_36XX_M2_26 0x09
++
++#define PER_36XX_M_38P4 0x1C2
++#define PER_36XX_N_38P4 0x13
++#define PER_36XX_FSEL_38P4 0x07
++#define PER_36XX_M2_38P4 0x09
++
+ #endif /* endif _CLOCKS_OMAP3_H_ */
+--
+1.6.6.1
+
--- /dev/null
+From 27c6c30dbb5de0c0ed30ceaf69bb0e9f12149c03 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 23 Mar 2010 09:21:49 -0700
+Subject: [PATCH 20/37] OMAP3: beagle: add support for Beagle xM
+
+---
+ board/ti/beagle/beagle.c | 23 +++++++++++++++--------
+ board/ti/beagle/beagle.h | 34 ++++++++++++++++++++++++++++++----
+ include/configs/omap3_beagle.h | 1 +
+ 3 files changed, 46 insertions(+), 12 deletions(-)
+
+diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
+index b4ea7e6..d357588 100644
+--- a/board/ti/beagle/beagle.c
++++ b/board/ti/beagle/beagle.c
+@@ -75,7 +75,7 @@ int beagle_get_revision(void)
+ * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
+ * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
+ * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
+- * GPIO173, GPIO172, GPIO171: 0 0 0 => D
++ * GPIO173, GPIO172, GPIO171: 0 0 0 => XM
+ */
+ void beagle_identify(void)
+ {
+@@ -108,29 +108,36 @@ int misc_init_r(void)
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+- printf("Board revision ");
+ switch (beagle_revision) {
+ case REVISION_AXBX:
+- printf("Ax/Bx\n");
++ printf("Beagle Rev Ax/Bx\n");
+ break;
+ case REVISION_CX:
+- printf("C1/C2/C3\n");
++ printf("Beagle Rev C1/C2/C3\n");
+ MUX_BEAGLE_C();
+ break;
+ case REVISION_C4:
+- printf("C4\n");
++ printf("Beagle Rev C4\n");
+ MUX_BEAGLE_C();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
++ setenv("mpurate", "720");
+ break;
+- case REVISION_D:
+- printf("D\n");
++ case REVISION_XM:
++ printf("Beagle xM Rev A\n");
++ MUX_BEAGLE_XM();
++ /* Set VAUX2 to 1.8V for EHCI PHY */
++ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
++ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
++ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
++ TWL4030_PM_RECEIVER_DEV_GRP_P1);
++ setenv("mpurate", "720");
+ break;
+ default:
+- printf("unknown 0x%02x\n", beagle_revision);
++ printf("Beagle unknown 0x%02x\n", beagle_revision);
+ }
+
+ /* Configure GPIOs to output */
+diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
+index d95fd78..fd06d46 100644
+--- a/board/ti/beagle/beagle.h
++++ b/board/ti/beagle/beagle.h
+@@ -38,7 +38,7 @@ const omap3_sysinfo sysinfo = {
+ #define REVISION_AXBX 0x7
+ #define REVISION_CX 0x6
+ #define REVISION_C4 0x5
+-#define REVISION_D 0x0
++#define REVISION_XM 0x0
+
+ /*
+ * IEN - Input Enable
+@@ -379,11 +379,37 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+ #define MUX_BEAGLE_C() \
+- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
+- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
+- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
++ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
++ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
++ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
+
++#define MUX_BEAGLE_XM() \
++ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
++ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
++ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
++ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
++ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
++ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
++ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
++ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
++ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
++ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
++ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
++ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
++ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
++ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
++ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
++ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
++ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
++ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
++ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
++ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
++ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
++ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
++ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
++ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
++
+ #endif
+diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
+index ce347cd..bba36df 100644
+--- a/include/configs/omap3_beagle.h
++++ b/include/configs/omap3_beagle.h
+@@ -157,6 +157,7 @@
+ /*
+ * Board NAND Info.
+ */
++#define CONFIG_SYS_NAND_QUIET_TEST 1
+ #define CONFIG_NAND_OMAP_GPMC
+ #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+--
+1.6.6.1
+
--- /dev/null
+From e26b222adeea78777a89e9b0d0aefed67cde7d55 Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Thu, 25 Mar 2010 06:54:47 -0700
+Subject: [PATCH 21/37] OMAP3: Beagle, Overo: remove omapfb.debug=y from default env
+
+---
+ include/configs/omap3_beagle.h | 2 --
+ include/configs/omap3_overo.h | 2 --
+ 2 files changed, 0 insertions(+), 4 deletions(-)
+
+diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
+index bba36df..c156cea 100644
+--- a/include/configs/omap3_beagle.h
++++ b/include/configs/omap3_beagle.h
+@@ -195,7 +195,6 @@
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+- "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+@@ -203,7 +202,6 @@
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+- "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
+index fdbeb67..418e2ea 100644
+--- a/include/configs/omap3_overo.h
++++ b/include/configs/omap3_overo.h
+@@ -164,7 +164,6 @@
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+- "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+@@ -172,7 +171,6 @@
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+- "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+--
+1.6.6.1
+
--- /dev/null
+From 851d35fab7f93400a1d714524b5e986206d9b0c4 Mon Sep 17 00:00:00 2001
+From: Koen Kooi <koen@dominion.thruhere.net>
+Date: Thu, 25 Mar 2010 16:07:23 +0100
+Subject: [PATCH 22/37] OMAP3: beagle: implement expansionboard detection based on board/overo.c code
+
+---
+ board/ti/beagle/beagle.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++
+ board/ti/beagle/beagle.h | 25 +++++++++++++-
+ 2 files changed, 101 insertions(+), 2 deletions(-)
+
+diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
+index d357588..8c5b88c 100644
+--- a/board/ti/beagle/beagle.c
++++ b/board/ti/beagle/beagle.c
+@@ -38,6 +38,31 @@
+ #include <asm/mach-types.h>
+ #include "beagle.h"
+
++static struct {
++ unsigned int device_vendor;
++ unsigned char revision;
++ unsigned char content;
++ unsigned char fab_revision[8];
++ unsigned char env_var[16];
++ unsigned char env_setting[64];
++} expansion_config;
++
++#define TWL4030_I2C_BUS 0
++
++#define EXPANSION_EEPROM_I2C_BUS 1
++#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
++
++#define TINCANTOOLS_VENDORID 0x0100
++#define GUMSTIX_VENDORID 0x0200
++#define SPECIALCOMP_VENDORID 0x0300
++
++#define TINCANTOOLS_ZIPPY 0x01000100
++#define TINCANTOOLS_ZIPPY2 0x02000100
++#define TINCANTOOLS_TRAINER 0x03000100
++#define TINCANTOOLS_SHOWDOG 0x04000100
++
++#define BEAGLE_NO_EEPROM 0xffffffff
++
+ static int beagle_revision;
+
+ /*
+@@ -95,6 +120,27 @@ void beagle_identify(void)
+ }
+
+ /*
++ * Routine: get_expansion_id
++ * Description: This function checks for expansion board by checking I2C
++ * bus 2 for the availability of an AT24C01B serial EEPROM.
++ * returns the device_vendor field from the EEPROM
++ */
++unsigned int get_expansion_id(void)
++{
++ i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
++
++ /* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
++ if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1)
++ return BEAGLE_NO_EEPROM;
++
++ /* read configuration data */
++ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
++ sizeof(expansion_config));
++
++ return expansion_config.device_vendor;
++}
++
++/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+@@ -104,6 +150,38 @@ int misc_init_r(void)
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
+ beagle_identify();
++ switch (get_expansion_id()) {
++ case TINCANTOOLS_ZIPPY:
++ printf("Recognized Tincantools Zippy expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.fab_revision);
++ MUX_TINCANTOOLS_ZIPPY();
++ break;
++ case TINCANTOOLS_ZIPPY2:
++ printf("Recognized Tincantools Zippy2 expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.fab_revision);
++ MUX_TINCANTOOLS_ZIPPY();
++ break;
++ case TINCANTOOLS_TRAINER:
++ printf("Recognized Tincantools Trainer expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.fab_revision);
++ break;
++ case TINCANTOOLS_SHOWDOG:
++ printf("Recognized Tincantools Showdow expansion board (rev %d %s)\n",
++ expansion_config.revision, expansion_config.fab_revision);
++ /* Place holder for DSS2 definition for showdog lcd */
++ setenv("defaultdisplay", "showdoglcd");
++ break;
++ case BEAGLE_NO_EEPROM:
++ printf("No EEPROM on expansion board\n");
++ break;
++ default:
++ printf("Unrecognized expansion board: %x\n", expansion_config.device_vendor);
++ }
++
++ if (expansion_config.content == 1)
++ setenv(expansion_config.env_var, expansion_config.env_setting);
++
++ i2c_set_bus_num(TWL4030_I2C_BUS);
+
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
+index fd06d46..ec4f831 100644
+--- a/board/ti/beagle/beagle.h
++++ b/board/ti/beagle/beagle.h
+@@ -260,8 +260,8 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
+- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
++ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
++ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+@@ -412,4 +412,25 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
+
++#define MUX_TINCANTOOLS_ZIPPY() \
++ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
++ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
++ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
++ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
++ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
++ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
++ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
++ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
++ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
++ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
++ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | EN | M1)) /*MCSPI4_CLK*/\
++ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
++ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M1)) /*MCSPI4_SIMO*/\
++ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
++ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) /*MCSPI4_CS0*/\
++ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
++ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
++ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
++ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
++
+ #endif
+--
+1.6.6.1
+
-From f62aac5842779fbc5a62ade1c78d47244d565456 Mon Sep 17 00:00:00 2001
+From 4b07f3a9f045453e5e7b5950e721ed35d9bd308a Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@dominion.thruhere.net>
Date: Wed, 31 Mar 2010 14:24:25 +0200
-Subject: [PATCH 01/14] beagleboard: display message about I2C errors being expected when no expansion boards are present
+Subject: [PATCH 23/37] beagleboard: display message about I2C errors being expected when no expansion boards are present
---
board/ti/beagle/beagle.c | 3 +++
-From d195df3a41a9614e150f517a25bf7b7f684bf05d Mon Sep 17 00:00:00 2001
+From a4fa85edf5ff6aa6a06f437acc8694dd866f6618 Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@dominion.thruhere.net>
Date: Sun, 11 Apr 2010 12:14:43 +0200
-Subject: [PATCH 02/14] beagleboard: fix TCT expansionboard IDs
+Subject: [PATCH 24/37] beagleboard: fix TCT expansionboard IDs
---
board/ti/beagle/beagle.c | 4 ++--
-From 53c3410ac7acae89c349cd1aa9b51fd81807dfd7 Mon Sep 17 00:00:00 2001
+From 10bffe78f0ef6cb450ecea717dce8d636982bc86 Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim <khasim@ti.com>
Date: Tue, 12 Jan 2010 23:57:28 +0530
-Subject: [PATCH 03/14] Add DSS driver for OMAP3
+Subject: [PATCH 25/37] Add DSS driver for OMAP3
Supports dynamic panel configuration
Supports dynamic tv standard selection
-From 907184b7135a2f954b905fdae8d1d6fff0d35744 Mon Sep 17 00:00:00 2001
+From a8adb8e29aba9d2c83731839063f1381fce3906c Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim <khasim@ti.com>
Date: Sun, 11 Apr 2010 17:44:39 +0200
-Subject: [PATCH 04/14] Enable DSS driver for Beagle
+Subject: [PATCH 26/37] Enable DSS driver for Beagle
Configures DSS to display color bar on Svideo
Configures DSS to display background color on DVID
-From 5a19707fed74b11a448c8467806b1cc038b449bc Mon Sep 17 00:00:00 2001
+From 85d4ffbc3a12b28cae00fc88d4adba7df4907fe4 Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@dominion.thruhere.net>
Date: Tue, 13 Apr 2010 22:04:07 +0200
-Subject: [PATCH 05/14] beagleboardXM: don't set mpurate on xM in bootargs
+Subject: [PATCH 27/37] beagleboardXM: don't set mpurate on xM in bootargs
---
board/ti/beagle/beagle.c | 1 -
-From 02ed9b6e7ddb60e440de346d56e77b9462f92d52 Mon Sep 17 00:00:00 2001
+From c18bda32fdb048ea38b7ff579f365ea8858053d7 Mon Sep 17 00:00:00 2001
From: Mans Rullgard <mans@mansr.com>
Date: Wed, 14 Apr 2010 12:08:00 +0100
-Subject: [PATCH 06/14] OMAP3: fix and clean up L2 cache enable/disable functions
+Subject: [PATCH 28/37] OMAP3: fix and clean up L2 cache enable/disable functions
On OMAP34xx ES1.0, the L2 enable bit can only be set in secure mode,
so an SMC call to the ROM monitor is required. On later versions,
-From 30ae6d713660fb415e6f253ec30cc0b2e5ffc2ee Mon Sep 17 00:00:00 2001
+From 6ddb5d4e28801907af7be39e47d502fd5c8e73e1 Mon Sep 17 00:00:00 2001
From: Mans Rullgard <mans@mansr.com>
Date: Wed, 14 Apr 2010 16:49:57 +0100
-Subject: [PATCH 07/14] OMAP3: convert setup_auxcr() to pure asm
+Subject: [PATCH 29/37] OMAP3: convert setup_auxcr() to pure asm
This function consists entirely of inline asm statements, so writing
it directly in a .S file is simpler. Additionally, the inline asm is
-From 2d0c47945ca49aa18dbedd9e4266ec18bc3b0150 Mon Sep 17 00:00:00 2001
+From 4e7bc59affc2a71de40259330e27e62181993968 Mon Sep 17 00:00:00 2001
From: Mans Rullgard <mans@mansr.com>
Date: Wed, 14 Apr 2010 17:10:28 +0100
-Subject: [PATCH 08/14] OMAP3: apply Cortex-A8 errata workarounds only on affected revisions
+Subject: [PATCH 30/37] OMAP3: apply Cortex-A8 errata workarounds only on affected revisions
The workarounds for errata 621766 and 725233 should only be applied
on affected Cortex-A8 revisions. Recent chips use r3px cores where
-From c5e5d27f80e389ddb8c7107e972b94c8d995dc84 Mon Sep 17 00:00:00 2001
+From bbfb38ccd1e2bb19a1eb698bd37cd1ab50c87b37 Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@dominion.thruhere.net>
Date: Fri, 23 Apr 2010 10:50:43 +0200
-Subject: [PATCH 09/14] OMAP3: beagle: add more expansionboards, based on http://www.elinux.org/BeagleBoardPinMux#Vendor_and_Device_IDs
+Subject: [PATCH 31/37] OMAP3: beagle: add more expansionboards, based on http://www.elinux.org/BeagleBoardPinMux#Vendor_and_Device_IDs
---
board/ti/beagle/beagle.c | 8 ++++++++
-From 3c116f300402f6375b7a8987b17962e125372d9d Mon Sep 17 00:00:00 2001
+From ae05ca488390671516bd4ed021eb43901fee740f Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@dominion.thruhere.net>
Date: Tue, 27 Apr 2010 13:44:16 +0200
-Subject: [PATCH 10/14] OMAP3: beagle: set mpurate to 600 for revB and revC1-3
+Subject: [PATCH 32/37] OMAP3: beagle: set mpurate to 600 for revB and revC1-3
---
board/ti/beagle/beagle.c | 2 ++
-From cd82c1f2db57407bc6571a3221937c14924cc440 Mon Sep 17 00:00:00 2001
+From caf18bc716d77d7bf2c75bc58ffbcbf09ae79f2b Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@dominion.thruhere.net>
Date: Tue, 27 Apr 2010 13:45:28 +0200
-Subject: [PATCH 11/14] OMAP3: beagle: prettify expansionboard message a bit
+Subject: [PATCH 33/37] OMAP3: beagle: prettify expansionboard message a bit
---
board/ti/beagle/beagle.c | 2 +-
-From f5796d9de9622ef47fff175613f1baf1d372b5ff Mon Sep 17 00:00:00 2001
+From 8580a3eafe3351e3c0f1ca3d0bc959bbeec40e28 Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@dominion.thruhere.net>
Date: Tue, 27 Apr 2010 18:25:57 +0200
-Subject: [PATCH 12/14] OMAP3: beagle: add pinmux for Tincantools Trainer expansionboard
+Subject: [PATCH 34/37] OMAP3: beagle: add pinmux for Tincantools Trainer expansionboard
---
board/ti/beagle/beagle.c | 2 ++
-From e1818be98d38ca515f3dd5be9bb6074fe0c6e564 Mon Sep 17 00:00:00 2001
+From c45e93aef4d54b262f0d8e1ecf6b111f5e1c2a4c Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@dominion.thruhere.net>
Date: Fri, 30 Apr 2010 13:25:41 +0200
-Subject: [PATCH 13/14] OMAP3: Beagle: set mpurate to 1000 for xM
+Subject: [PATCH 35/37] OMAP3: Beagle: set mpurate to 1000 for xM
---
board/ti/beagle/beagle.c | 1 +
-From 94ea631bf18a242660a1c3e6e028409480217837 Mon Sep 17 00:00:00 2001
+From 39f15722db5595411ec085e36b7fd7657415a554 Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@dominion.thruhere.net>
Date: Fri, 30 Apr 2010 13:26:01 +0200
-Subject: [PATCH 14/14] OMAP3: Beagle: decrease bootdelay to 3, use VGA for default resolution
+Subject: [PATCH 36/37] OMAP3: Beagle: decrease bootdelay to 3, use VGA for default resolution
---
include/configs/omap3_beagle.h | 4 ++--
--- /dev/null
+From 8ad472139f7b8b7c59c0192f3e2f50a20beadf59 Mon Sep 17 00:00:00 2001
+From: Koen Kooi <koen@dominion.thruhere.net>
+Date: Mon, 3 May 2010 10:17:41 +0200
+Subject: [PATCH 37/37] OMAP3: beagle: pass expansionboard name in bootargs
+
+This makes it possible to do in-kernel fixups for expansionboards like reclaiming GPIOs
+---
+ board/ti/beagle/beagle.c | 7 +++++++
+ include/configs/omap3_beagle.h | 3 +++
+ 2 files changed, 10 insertions(+), 0 deletions(-)
+
+diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
+index 9300984..556e995 100644
+--- a/board/ti/beagle/beagle.c
++++ b/board/ti/beagle/beagle.c
+@@ -172,33 +172,40 @@ int misc_init_r(void)
+ printf("Recognized Tincantools Zippy expansion board (rev %d %s)\n",
+ expansion_config.revision, expansion_config.fab_revision);
+ MUX_TINCANTOOLS_ZIPPY();
++ setenv("buddy", "zippy");
+ break;
+ case TINCANTOOLS_ZIPPY2:
+ printf("Recognized Tincantools Zippy2 expansion board (rev %d %s)\n",
+ expansion_config.revision, expansion_config.fab_revision);
+ MUX_TINCANTOOLS_ZIPPY();
++ setenv("buddy", "zippy2");
+ break;
+ case TINCANTOOLS_TRAINER:
+ printf("Recognized Tincantools Trainer expansion board (rev %d %s)\n",
+ expansion_config.revision, expansion_config.fab_revision);
+ MUX_TINCANTOOLS_ZIPPY();
+ MUX_TINCANTOOLS_TRAINER();
++ setenv("buddy", "trainer");
+ break;
+ case TINCANTOOLS_SHOWDOG:
+ printf("Recognized Tincantools Showdow expansion board (rev %d %s)\n",
+ expansion_config.revision, expansion_config.fab_revision);
+ /* Place holder for DSS2 definition for showdog lcd */
+ setenv("defaultdisplay", "showdoglcd");
++ setenv("buddy", "showdog");
+ break;
+ case KBADC_BEAGLEFPGA:
+ printf("Recognized KBADC Beagle FPGA board\n");
+ MUX_KBADC_BEAGLEFPGA();
++ setenv("buddy", "beaglefpga");
+ break;
+ case BEAGLE_NO_EEPROM:
+ printf("No EEPROM on expansion board\n");
++ setenv("buddy", "none");
+ break;
+ default:
+ printf("Unrecognized expansion board: %x\n", expansion_config.device_vendor);
++ setenv("buddy", "unknown");
+ }
+
+ if (expansion_config.content == 1)
+diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
+index 93a6a5a..affabf1 100644
+--- a/include/configs/omap3_beagle.h
++++ b/include/configs/omap3_beagle.h
+@@ -185,6 +185,7 @@
+ "usbtty=cdc_acm\0" \
+ "console=ttyS2,115200n8\0" \
+ "mpurate=500\0" \
++ "buddy=none\0" \
+ "vram=12M\0" \
+ "dvimode=640x480MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+@@ -194,6 +195,7 @@
+ "nandrootfstype=jffs2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
++ "buddy=${buddy} "\
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapdss.def_disp=${defaultdisplay} " \
+@@ -201,6 +203,7 @@
+ "rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
++ "buddy=${buddy} "\
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapdss.def_disp=${defaultdisplay} " \
+--
+1.6.6.1
+
require u-boot.inc
-PR ="r48"
+PR ="r49"
FILESPATHPKG =. "u-boot-git:"
SRC_URI_append_afeb9260-180 = " file://AFEB9260-network-fix.patch;patch=1"
SRC_URI_append_cm-t35 = "file://cm-t35/cm-t35.patch;patch=1"
-SRC_URI_beagleboard = "git://www.sakoman.com/git/u-boot.git;branch=omap3-v2010.3;protocol=git \
- file://0001-beagleboard-display-message-about-I2C-errors-being-e.patch;patch=1 \
- file://0002-beagleboard-fix-TCT-expansionboard-IDs.patch;patch=1 \
- file://0003-Add-DSS-driver-for-OMAP3.patch;patch=1 \
- file://0004-Enable-DSS-driver-for-Beagle.patch;patch=1 \
- file://0005-beagleboardXM-don-t-set-mpurate-on-xM-in-bootargs.patch;patch=1 \
- file://0006-OMAP3-fix-and-clean-up-L2-cache-enable-disable-funct.patch;patch=1 \
- file://0007-OMAP3-convert-setup_auxcr-to-pure-asm.patch;patch=1 \
- file://0008-OMAP3-apply-Cortex-A8-errata-workarounds-only-on-aff.patch;patch=1 \
- file://0009-OMAP3-beagle-add-more-expansionboards-based-on-http-.patch;patch=1 \
- file://0010-OMAP3-beagle-set-mpurate-to-600-for-revB-and-revC1-3.patch;patch=1 \
- file://0011-OMAP3-beagle-prettify-expansionboard-message-a-bit.patch;patch=1 \
- file://0012-OMAP3-beagle-add-pinmux-for-Tincantools-Trainer-expa.patch;patch=1 \
- file://0013-OMAP3-Beagle-set-mpurate-to-1000-for-xM.patch;patch=1 \
- file://0014-OMAP3-Beagle-decrease-bootdelay-to-3-use-VGA-for-def.patch;patch=1 \
+SRC_URI_beagleboard = "git://www.denx.de/git/u-boot.git;protocol=git \
+ file://0001-OMAP3-enable-i2c-bus-switching-for-Beagle-and-Overo.patch;patch=1 \
+ file://0002-OMAP3-add-board-revision-detection-for-Overo.patch;patch=1 \
+ file://0003-OMAP3-update-Beagle-revision-detection-to-recognize-.patch;patch=1 \
+ file://0004-OMAP3-Set-VAUX2-to-1.8V-for-EHCI-PHY-on-Beagle-Rev-C.patch;patch=1 \
+ file://0005-OMAP3-add-entry-for-rev-3.1.2-check-and-display-max-.patch;patch=1 \
+ file://0006-OMAP3-add-mpurate-boot-arg-for-overo-and-beagle.patch;patch=1 \
+ file://0007-OMAP3-detect-expansion-board-type-version-using-eepr.patch;patch=1 \
+ file://0008-OMAP3-Overo-enable-config-eeprom-to-set-u-boot-env-v.patch;patch=1 \
+ file://0009-OMAP3-Overo-enable-input-on-MMC1_CLK-and-MMC3_CLK-pi.patch;patch=1 \
+ file://0010-OMAP3-Overo-set-CONFIG_SYS_I2C_SPEED-to-400Khz.patch;patch=1 \
+ file://0011-OMAP3-trim-excessively-long-delays-in-i2c-driver.patch;patch=1 \
+ file://0012-OMAP3-Overo-allow-expansion-boards-with-any-vendor-I.patch;patch=1 \
+ file://0013-OMAP3-Overo-change-address-of-expansion-eeprom-to-0x.patch;patch=1 \
+ file://0014-OMAP3-board.c-don-t-attempt-to-set-up-second-RAM-ban.patch;patch=1 \
+ file://0015-OMAP3-mem.c-enhance-the-RAM-test.patch;patch=1 \
+ file://0016-env_nand.c-fail-gracefully-if-no-nand-is-present.patch;patch=1 \
+ file://0017-OMAP3-add-definitions-to-support-sysinfo-cpu-and-cpu.patch;patch=1 \
+ file://0018-OMAP3-sys_info-update-cpu-detection-for-36XX-37XX.patch;patch=1 \
+ file://0019-OMAP3-clocks-update-clock-setup-for-36XX-37XX.patch;patch=1 \
+ file://0020-OMAP3-beagle-add-support-for-Beagle-xM.patch;patch=1 \
+ file://0021-OMAP3-Beagle-Overo-remove-omapfb.debug-y-from-defaul.patch;patch=1 \
+ file://0022-OMAP3-beagle-implement-expansionboard-detection-base.patch;patch=1 \
+ file://0023-beagleboard-display-message-about-I2C-errors-being-e.patch;patch=1 \
+ file://0024-beagleboard-fix-TCT-expansionboard-IDs.patch;patch=1 \
+ file://0025-Add-DSS-driver-for-OMAP3.patch;patch=1 \
+ file://0026-Enable-DSS-driver-for-Beagle.patch;patch=1 \
+ file://0027-beagleboardXM-don-t-set-mpurate-on-xM-in-bootargs.patch;patch=1 \
+ file://0028-OMAP3-fix-and-clean-up-L2-cache-enable-disable-funct.patch;patch=1 \
+ file://0029-OMAP3-convert-setup_auxcr-to-pure-asm.patch;patch=1 \
+ file://0030-OMAP3-apply-Cortex-A8-errata-workarounds-only-on-aff.patch;patch=1 \
+ file://0031-OMAP3-beagle-add-more-expansionboards-based-on-http-.patch;patch=1 \
+ file://0032-OMAP3-beagle-set-mpurate-to-600-for-revB-and-revC1-3.patch;patch=1 \
+ file://0033-OMAP3-beagle-prettify-expansionboard-message-a-bit.patch;patch=1 \
+ file://0034-OMAP3-beagle-add-pinmux-for-Tincantools-Trainer-expa.patch;patch=1 \
+ file://0035-OMAP3-Beagle-set-mpurate-to-1000-for-xM.patch;patch=1 \
+ file://0036-OMAP3-Beagle-decrease-bootdelay-to-3-use-VGA-for-def.patch;patch=1 \
+ file://0037-OMAP3-beagle-pass-expansionboard-name-in-bootargs.patch;patch=1 \
file://fw_env.config \
"
-SRCREV_beagleboard = "946351081bd14e8bf5816fc38b82e004a0e6b4fe"
-PV_beagleboard = "2010.03-rc1+${PR}+gitr${SRCREV}"
+SRCREV_beagleboard = "ca6e1c136ddb720c3bb2cc043b99f7f06bc46c55"
+PV_beagleboard = "2010.03+${PR}+gitr${SRCREV}"
SRCREV_calamari = "533cf3a024947aaf74c16573a6d951cd0c3d0a7d"
git.openpandora.org / openembedded.git / commitdiff