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ath5k: update AR5K_PHY_RESTART_DIV_GC values to match masks
authorBruno Randolf <br1@einfach.org>
Mon, 7 Jun 2010 04:11:25 +0000 (13:11 +0900)
committerJohn W. Linville <linville@tuxdriver.com>
Tue, 8 Jun 2010 13:31:20 +0000 (09:31 -0400)
#define AR5K_PHY_RESTART_DIV_GC               0x001c0000
is 3 bit wide.

The previous values of 0xc and 0x8 are 4bit wide and bigger than the mask.

Writing 0 and 1 to AR5K_PHY_RESTART_DIV_GC is consistent with the comments and
initvals we have in the HAL.

Signed-off-by: Bruno Randolf <br1@einfach.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

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