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ARM: 5791/1: ARM: MM: use 64bytes of L1 cache on plat S5PC1xx
authorMarek Szyprowski <m.szyprowski@samsung.com>
Thu, 19 Nov 2009 10:30:30 +0000 (11:30 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Tue, 24 Nov 2009 10:06:26 +0000 (10:06 +0000)
Samsung S5PC1xx SoCs are based on ARM Coretex8, which has 64 bytes of L1
cache line size. Enable proper handling of L1 cache on these SoCs.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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