clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain

This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>

diff --cc drivers/clk/samsung/clk-exynos5250.c
Simple merge