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ASoC: Fix WM8996 24.576MHz clock operation
authorMark Brown <broonie@opensource.wolfsonmicro.com>
Sat, 10 Dec 2011 12:38:32 +0000 (20:38 +0800)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Sat, 10 Dec 2011 19:01:09 +0000 (03:01 +0800)
Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org

No differences found
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