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spi/fsl-espi: make the clock computation easier to read
authorSebastian Andrzej Siewior <bigeasy@linutronix.de>
Thu, 15 Mar 2012 17:42:31 +0000 (18:42 +0100)
committerGrant Likely <grant.likely@secretlab.ca>
Thu, 15 Mar 2012 21:14:13 +0000 (15:14 -0600)
The -1 +1 thingy should probably do what DIV_ROUND_UP does. The 4 is 2
the  "platform_clock => sysclock" and 2 from the computation part. The 64
is the same 4 times 16.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

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