#define CCU_PRCM_PLL_LDO_CFG 0x244
#define CCU_PRCM_SYS_PWROFF_GATING 0x250
#define CCU_PRCM_RES_CAL_CTRL 0x310
+#define CCU_PRCM_OHMS240 0x318
struct sunxi_prcm_reg {
u32 cpus_cfg; /* 0x000 */
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_prcm_reg *const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ void *const prcm = (void *)SUNXI_PRCM_BASE;
struct dram_config config;
-
unsigned long size;
- setbits_le32(&prcm->res_cal_ctrl, BIT(8));
- clrbits_le32(&prcm->ohms240, 0x3f);
+ setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8));
+ clrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f);
mctl_auto_detect_rank_width(¶, &config);
mctl_auto_detect_dram_size(¶, &config);
unsigned long sunxi_dram_init(void)
{
- struct sunxi_prcm_reg *const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ void *const prcm = (void *)SUNXI_PRCM_BASE;
struct dram_config config;
unsigned long size;
- setbits_le32(&prcm->res_cal_ctrl, BIT(8));
- clrbits_le32(&prcm->ohms240, 0x3f);
+ setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8));
+ clrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f);
mctl_auto_detect_rank_width(¶, &config);
mctl_auto_detect_dram_size(¶, &config);