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video: exynos_dp: Fix incorrect setting for INT_CTL
authorAjay Kumar <ajaykumar.rs@samsung.com>
Mon, 5 Nov 2012 07:47:00 +0000 (16:47 +0900)
committerJingoo Han <jg1.han@samsung.com>
Thu, 29 Nov 2012 01:33:28 +0000 (10:33 +0900)
INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL.
This patch fixes the wrong register setting for INT_CTL.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>

No differences found
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