cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREA_EXT);
if (cadence_nand_dma_buf_ok(cadence, buf, mtd->writesize) &&
- cadence->caps2.data_control_supp) {
+ cadence->caps2.data_control_supp && !(chip->options & NAND_USE_BOUNCE_BUFFER)) {
u8 *oob;
if (oob_required)
* is supported then transfer data and oob directly.
*/
if (cadence_nand_dma_buf_ok(cadence, buf, mtd->writesize) &&
- cadence->caps2.data_control_supp) {
+ cadence->caps2.data_control_supp && !(chip->options & NAND_USE_BOUNCE_BUFFER)) {
u8 *oob;
if (oob_required)
return ret;
}
+ chip->options |= NAND_USE_BOUNCE_BUFFER;
chip->bbt_options |= NAND_BBT_USE_FLASH;
chip->bbt_options |= NAND_BBT_NO_OOB;
chip->ecc.mode = NAND_ECC_HW_SYNDROME;