Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (46 commits)
  random: simplify fips mode
  crypto: authenc - Fix cryptlen calculation
  crypto: talitos - add support for sha224
  crypto: talitos - add hash algorithms
  crypto: talitos - second prepare step for adding ahash algorithms
  crypto: talitos - prepare for adding ahash algorithms
  crypto: n2 - Add Niagara2 crypto driver
  crypto: skcipher - Add ablkcipher_walk interfaces
  crypto: testmgr - Add testing for async hashing and update/final
  crypto: tcrypt - Add speed tests for async hashing
  crypto: scatterwalk - Fix scatterwalk_done() test
  crypto: hifn_795x - Rename ablkcipher_walk to hifn_cipher_walk
  padata: Use get_online_cpus/put_online_cpus in padata_free
  padata: Add some code comments
  padata: Flush the padata queues actively
  padata: Use a timer to handle remaining objects in the reorder queues
  crypto: shash - Remove usage of CRYPTO_MINALIGN
  crypto: mv_cesa - Use resource_size
  crypto: omap - OMAP macros corrected
  padata: Use get_online_cpus/put_online_cpus
  ...

Fix up conflicts in arch/arm/mach-omap2/devices.c

diff --combined arch/arm/mach-omap2/clock2420_data.c
index 23bc981,1820a55..37d65d6
--- 1/arch/arm/mach-omap2/clock2420_data.c
--- 2/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@@ -155,12 -155,12 +155,12 @@@ static struct clk apll54_ck = 
  /* func_54m_ck */
  
  static const struct clksel_rate func_54m_apll54_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
  
  static const struct clksel_rate func_54m_alt_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
  
@@@ -177,7 -177,7 +177,7 @@@ static struct clk func_54m_ck = 
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 -      .clksel_mask    = OMAP24XX_54M_SOURCE,
 +      .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
        .clksel         = func_54m_clksel,
        .recalc         = &omap2_clksel_recalc,
  };
@@@ -201,12 -201,12 +201,12 @@@ static struct clk func_96m_ck = 
  /* func_48m_ck */
  
  static const struct clksel_rate func_48m_apll96_rates[] = {
 -      { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 2, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
  
  static const struct clksel_rate func_48m_alt_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
  
@@@ -223,7 -223,7 +223,7 @@@ static struct clk func_48m_ck = 
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 -      .clksel_mask    = OMAP24XX_48M_SOURCE,
 +      .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
        .clksel         = func_48m_clksel,
        .recalc         = &omap2_clksel_recalc,
        .round_rate     = &omap2_clksel_round_rate,
@@@ -256,22 -256,22 +256,22 @@@ static struct clk wdt1_osc_ck = 
   * flags fields, which mark them as 2420-only.
   */
  static const struct clksel_rate common_clkout_src_core_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
  static const struct clksel_rate common_clkout_src_sys_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
  static const struct clksel_rate common_clkout_src_96m_rates[] = {
 -      { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 2, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
  static const struct clksel_rate common_clkout_src_54m_rates[] = {
 -      { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 3, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
@@@ -300,7 -300,7 +300,7 @@@ static struct clk sys_clkout_src = 
  };
  
  static const struct clksel_rate common_clkout_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 2, .val = 1, .flags = RATE_IN_24XX },
        { .div = 4, .val = 2, .flags = RATE_IN_24XX },
        { .div = 8, .val = 3, .flags = RATE_IN_24XX },
@@@ -384,7 -384,7 +384,7 @@@ static struct clk emul_ck = 
   *
   */
  static const struct clksel_rate mpu_core_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 4, .val = 4, .flags = RATE_IN_242X },
        { .div = 6, .val = 6, .flags = RATE_IN_242X },
@@@ -420,7 -420,7 +420,7 @@@ static struct clk mpu_ck = {       /* Contro
   * routed into a synchronizer and out of clocks abc.
   */
  static const struct clksel_rate dsp_fck_core_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
@@@ -450,7 -450,7 +450,7 @@@ static struct clk dsp_fck = 
  
  /* DSP interface clock */
  static const struct clksel_rate dsp_irate_ick_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
@@@ -532,7 -532,7 +532,7 @@@ static struct clk iva1_mpu_int_ifck = 
  static const struct clksel_rate core_l3_core_rates[] = {
        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 2, .val = 2, .flags = RATE_IN_242X },
 -      { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 4, .val = 4, .flags = RATE_IN_24XX },
        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
        { .div = 8, .val = 8, .flags = RATE_IN_242X },
        { .div = 12, .val = 12, .flags = RATE_IN_242X },
@@@ -559,7 -559,7 +559,7 @@@ static struct clk core_l3_ck = {   /* Use
  /* usb_l4_ick */
  static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 -      { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
@@@ -591,7 -591,7 +591,7 @@@ static struct clk usb_l4_ick = {   /* FS-
   * this domain.
   */
  static const struct clksel_rate l4_core_l3_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
@@@ -622,7 -622,7 +622,7 @@@ static struct clk l4_ck = {                /* used bo
   */
  static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 -      { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
        { .div = 6, .val = 6, .flags = RATE_IN_242X },
@@@ -730,7 -730,7 +730,7 @@@ static struct clk gfx_ick = 
  /* XXX Add RATE_NOT_VALIDATED */
  
  static const struct clksel_rate dss1_fck_sys_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
@@@ -744,7 -744,7 +744,7 @@@ static const struct clksel_rate dss1_fc
        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
 -      { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 16, .val = 16, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
@@@ -779,12 -779,12 +779,12 @@@ static struct clk dss1_fck = 
  };
  
  static const struct clksel_rate dss2_fck_sys_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
  static const struct clksel_rate dss2_fck_48m_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
@@@ -825,7 -825,7 +825,7 @@@ static struct clk dss_54m_fck = {  /* Al
   * functional clock parents.
   */
  static const struct clksel_rate gpt_alt_rates[] = {
 -      { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 2, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
@@@ -1588,7 -1588,7 +1588,7 @@@ static struct clk vlynq_ick = 
  };
  
  static const struct clksel_rate vlynq_fck_96m_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_242X },
        { .div = 0 }
  };
  
@@@ -1601,7 -1601,7 +1601,7 @@@ static const struct clksel_rate vlynq_f
        { .div = 8, .val = 8, .flags = RATE_IN_242X },
        { .div = 9, .val = 9, .flags = RATE_IN_242X },
        { .div = 12, .val = 12, .flags = RATE_IN_242X },
 -      { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
 +      { .div = 16, .val = 16, .flags = RATE_IN_242X },
        { .div = 18, .val = 18, .flags = RATE_IN_242X },
        { .div = 0 }
  };
@@@ -1836,7 -1836,7 +1836,7 @@@ static struct omap_clk omap2420_clks[] 
        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
        CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
-       CLK(NULL,       "sha_ick",      &sha_ick,       CK_242X),
+       CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
        CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
        CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),

diff --combined arch/arm/mach-omap2/clock2430_data.c
index 2df50d9,5884ac6..b33118f
--- 1/arch/arm/mach-omap2/clock2430_data.c
--- 2/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@@ -155,12 -155,12 +155,12 @@@ static struct clk apll54_ck = 
  /* func_54m_ck */
  
  static const struct clksel_rate func_54m_apll54_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
  
  static const struct clksel_rate func_54m_alt_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
  
@@@ -177,7 -177,7 +177,7 @@@ static struct clk func_54m_ck = 
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 -      .clksel_mask    = OMAP24XX_54M_SOURCE,
 +      .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
        .clksel         = func_54m_clksel,
        .recalc         = &omap2_clksel_recalc,
  };
@@@ -192,12 -192,12 +192,12 @@@ static struct clk core_ck = 
  
  /* func_96m_ck */
  static const struct clksel_rate func_96m_apll96_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
  
  static const struct clksel_rate func_96m_alt_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_243X },
        { .div = 0 },
  };
  
@@@ -214,7 -214,7 +214,7 @@@ static struct clk func_96m_ck = 
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 -      .clksel_mask    = OMAP2430_96M_SOURCE,
 +      .clksel_mask    = OMAP2430_96M_SOURCE_MASK,
        .clksel         = func_96m_clksel,
        .recalc         = &omap2_clksel_recalc,
  };
@@@ -222,12 -222,12 +222,12 @@@
  /* func_48m_ck */
  
  static const struct clksel_rate func_48m_apll96_rates[] = {
 -      { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 2, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
  
  static const struct clksel_rate func_48m_alt_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
  
@@@ -244,7 -244,7 +244,7 @@@ static struct clk func_48m_ck = 
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 -      .clksel_mask    = OMAP24XX_48M_SOURCE,
 +      .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
        .clksel         = func_48m_clksel,
        .recalc         = &omap2_clksel_recalc,
        .round_rate     = &omap2_clksel_round_rate,
@@@ -277,22 -277,22 +277,22 @@@ static struct clk wdt1_osc_ck = 
   * flags fields, which mark them as 2420-only.
   */
  static const struct clksel_rate common_clkout_src_core_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
  static const struct clksel_rate common_clkout_src_sys_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
  static const struct clksel_rate common_clkout_src_96m_rates[] = {
 -      { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 2, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
  static const struct clksel_rate common_clkout_src_54m_rates[] = {
 -      { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 3, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
@@@ -321,7 -321,7 +321,7 @@@ static struct clk sys_clkout_src = 
  };
  
  static const struct clksel_rate common_clkout_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 2, .val = 1, .flags = RATE_IN_24XX },
        { .div = 4, .val = 2, .flags = RATE_IN_24XX },
        { .div = 8, .val = 3, .flags = RATE_IN_24XX },
@@@ -369,7 -369,7 +369,7 @@@ static struct clk emul_ck = 
   *
   */
  static const struct clksel_rate mpu_core_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 0 },
  };
@@@ -402,7 -402,7 +402,7 @@@ static struct clk mpu_ck = {       /* Contro
   * routed into a synchronizer and out of clocks abc.
   */
  static const struct clksel_rate dsp_fck_core_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
@@@ -429,7 -429,7 +429,7 @@@ static struct clk dsp_fck = 
  
  /* DSP interface clock */
  static const struct clksel_rate dsp_irate_ick_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 3, .val = 3, .flags = RATE_IN_243X },
        { .div = 0 },
@@@ -481,7 -481,7 +481,7 @@@ static struct clk iva2_1_ick = 
   */
  static const struct clksel_rate core_l3_core_rates[] = {
        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 -      { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 4, .val = 4, .flags = RATE_IN_24XX },
        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
@@@ -505,7 -505,7 +505,7 @@@ static struct clk core_l3_ck = {   /* Use
  /* usb_l4_ick */
  static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 -      { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
@@@ -537,7 -537,7 +537,7 @@@ static struct clk usb_l4_ick = {   /* FS-
   * this domain.
   */
  static const struct clksel_rate l4_core_l3_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
@@@ -568,7 -568,7 +568,7 @@@ static struct clk l4_ck = {                /* used bo
   */
  static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 -      { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 2, .val = 2, .flags = RATE_IN_24XX },
        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
        { .div = 5, .val = 5, .flags = RATE_IN_243X },
@@@ -673,7 -673,7 +673,7 @@@ static struct clk gfx_ick = 
   */
  static const struct clksel_rate mdm_ick_core_rates[] = {
        { .div = 1, .val = 1, .flags = RATE_IN_243X },
 -      { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
 +      { .div = 4, .val = 4, .flags = RATE_IN_243X },
        { .div = 6, .val = 6, .flags = RATE_IN_243X },
        { .div = 9, .val = 9, .flags = RATE_IN_243X },
        { .div = 0 }
@@@ -718,7 -718,7 +718,7 @@@ static struct clk mdm_osc_ck = 
  /* XXX Add RATE_NOT_VALIDATED */
  
  static const struct clksel_rate dss1_fck_sys_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
@@@ -732,7 -732,7 +732,7 @@@ static const struct clksel_rate dss1_fc
        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
 -      { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 16, .val = 16, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
@@@ -767,12 -767,12 +767,12 @@@ static struct clk dss1_fck = 
  };
  
  static const struct clksel_rate dss2_fck_sys_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
  static const struct clksel_rate dss2_fck_48m_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
@@@ -813,7 -813,7 +813,7 @@@ static struct clk dss_54m_fck = {  /* Al
   * functional clock parents.
   */
  static const struct clksel_rate gpt_alt_rates[] = {
 -      { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 +      { .div = 1, .val = 2, .flags = RATE_IN_24XX },
        { .div = 0 }
  };
  
@@@ -1924,7 -1924,7 +1924,7 @@@ static struct omap_clk omap2430_clks[] 
        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
        CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
-       CLK(NULL,       "sha_ick",      &sha_ick,       CK_243X),
+       CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
        CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
        CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X),
        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),

diff --combined arch/arm/mach-omap2/clock3xxx_data.c
index 833be48,52638df..41b155a
--- 1/arch/arm/mach-omap2/clock3xxx_data.c
--- 2/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@@ -110,32 -110,32 +110,32 @@@ static struct clk virt_38_4m_ck = 
  };
  
  static const struct clksel_rate osc_sys_12m_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate osc_sys_13m_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate osc_sys_16_8m_rates[] = {
 -      { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 +      { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
        { .div = 0 }
  };
  
  static const struct clksel_rate osc_sys_19_2m_rates[] = {
 -      { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate osc_sys_26m_rates[] = {
 -      { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate osc_sys_38_4m_rates[] = {
 -      { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
@@@ -163,8 -163,8 +163,8 @@@ static struct clk osc_sys_ck = 
  };
  
  static const struct clksel_rate div2_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 2, .val = 2, .flags = RATE_IN_343X },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 +      { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
@@@ -213,42 -213,42 +213,42 @@@ static struct clk sys_clkout1 = 
  /* CM CLOCKS */
  
  static const struct clksel_rate div16_dpll_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 2, .val = 2, .flags = RATE_IN_343X },
 -      { .div = 3, .val = 3, .flags = RATE_IN_343X },
 -      { .div = 4, .val = 4, .flags = RATE_IN_343X },
 -      { .div = 5, .val = 5, .flags = RATE_IN_343X },
 -      { .div = 6, .val = 6, .flags = RATE_IN_343X },
 -      { .div = 7, .val = 7, .flags = RATE_IN_343X },
 -      { .div = 8, .val = 8, .flags = RATE_IN_343X },
 -      { .div = 9, .val = 9, .flags = RATE_IN_343X },
 -      { .div = 10, .val = 10, .flags = RATE_IN_343X },
 -      { .div = 11, .val = 11, .flags = RATE_IN_343X },
 -      { .div = 12, .val = 12, .flags = RATE_IN_343X },
 -      { .div = 13, .val = 13, .flags = RATE_IN_343X },
 -      { .div = 14, .val = 14, .flags = RATE_IN_343X },
 -      { .div = 15, .val = 15, .flags = RATE_IN_343X },
 -      { .div = 16, .val = 16, .flags = RATE_IN_343X },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 +      { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 +      { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 +      { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 +      { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 +      { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 +      { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 +      { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 +      { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 +      { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 +      { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 +      { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 +      { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 +      { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 +      { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 +      { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
 -static const struct clksel_rate div32_dpll4_rates_3630[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE },
 -      { .div = 2, .val = 2, .flags = RATE_IN_36XX },
 -      { .div = 3, .val = 3, .flags = RATE_IN_36XX },
 -      { .div = 4, .val = 4, .flags = RATE_IN_36XX },
 -      { .div = 5, .val = 5, .flags = RATE_IN_36XX },
 -      { .div = 6, .val = 6, .flags = RATE_IN_36XX },
 -      { .div = 7, .val = 7, .flags = RATE_IN_36XX },
 -      { .div = 8, .val = 8, .flags = RATE_IN_36XX },
 -      { .div = 9, .val = 9, .flags = RATE_IN_36XX },
 -      { .div = 10, .val = 10, .flags = RATE_IN_36XX },
 -      { .div = 11, .val = 11, .flags = RATE_IN_36XX },
 -      { .div = 12, .val = 12, .flags = RATE_IN_36XX },
 -      { .div = 13, .val = 13, .flags = RATE_IN_36XX },
 -      { .div = 14, .val = 14, .flags = RATE_IN_36XX },
 -      { .div = 15, .val = 15, .flags = RATE_IN_36XX },
 -      { .div = 16, .val = 16, .flags = RATE_IN_36XX },
 +static const struct clksel_rate dpll4_rates[] = {
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 +      { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 +      { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 +      { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 +      { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 +      { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 +      { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 +      { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 +      { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 +      { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 +      { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 +      { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 +      { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 +      { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 +      { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 +      { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
        { .div = 17, .val = 17, .flags = RATE_IN_36XX },
        { .div = 18, .val = 18, .flags = RATE_IN_36XX },
        { .div = 19, .val = 19, .flags = RATE_IN_36XX },
@@@ -450,37 -450,37 +450,37 @@@ static struct clk dpll3_x2_ck = 
  };
  
  static const struct clksel_rate div31_dpll3_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 2, .val = 2, .flags = RATE_IN_343X },
 -      { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 -      { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 -      { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 -      { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 -      { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 -      { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 -      { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 -      { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 -      { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 -      { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 -      { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 -      { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 -      { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 -      { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 -      { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 -      { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 -      { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 -      { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 -      { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 -      { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 -      { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 -      { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 -      { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 -      { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 -      { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 -      { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 -      { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 -      { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 -      { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 +      { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 +      { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
 +      { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
        { .div = 0 },
  };
  
@@@ -562,7 -562,6 +562,7 @@@ static struct clk emu_core_alwon_ck = 
  /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
  /* Type: DPLL */
  static struct dpll_data dpll4_dd;
 +
  static struct dpll_data dpll4_dd_34xx __initdata = {
        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
@@@ -633,20 -632,39 +633,20 @@@ static struct clk dpll4_x2_ck = 
        .recalc         = &omap3_clkoutx2_recalc,
  };
  
 -static const struct clksel div16_dpll4_clksel[] = {
 -      { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 -      { .parent = NULL }
 -};
 -
 -static const struct clksel div32_dpll4_clksel[] = {
 -      { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
 +static const struct clksel dpll4_clksel[] = {
 +      { .parent = &dpll4_ck, .rates = dpll4_rates },
        { .parent = NULL }
  };
  
  /* This virtual clock is the source for dpll4_m2x2_ck */
 -static struct clk dpll4_m2_ck;
 -
 -static struct clk dpll4_m2_ck_34xx __initdata = {
 -      .name           = "dpll4_m2_ck",
 -      .ops            = &clkops_null,
 -      .parent         = &dpll4_ck,
 -      .init           = &omap2_init_clksel_parent,
 -      .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 -      .clksel_mask    = OMAP3430_DIV_96M_MASK,
 -      .clksel         = div16_dpll4_clksel,
 -      .clkdm_name     = "dpll4_clkdm",
 -      .recalc         = &omap2_clksel_recalc,
 -};
 -
 -static struct clk dpll4_m2_ck_3630 __initdata  = {
 +static struct clk dpll4_m2_ck = {
        .name           = "dpll4_m2_ck",
        .ops            = &clkops_null,
        .parent         = &dpll4_ck,
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
        .clksel_mask    = OMAP3630_DIV_96M_MASK,
 -      .clksel         = div32_dpll4_clksel,
 +      .clksel         = dpll4_clksel,
        .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
  };
@@@ -680,7 -698,7 +680,7 @@@ static struct clk omap_192m_alwon_fck 
  
  static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
        { .div = 1, .val = 1, .flags = RATE_IN_36XX },
 -      { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE },
 +      { .div = 2, .val = 2, .flags = RATE_IN_36XX },
        { .div = 0 }
  };
  
@@@ -690,12 -708,12 +690,12 @@@ static const struct clksel omap_96m_alw
  };
  
  static const struct clksel_rate omap_96m_dpll_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate omap_96m_sys_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
@@@ -742,14 -760,28 +742,14 @@@ static struct clk omap_96m_fck = 
  };
  
  /* This virtual clock is the source for dpll4_m3x2_ck */
 -static struct clk dpll4_m3_ck;
 -
 -static struct clk dpll4_m3_ck_34xx __initdata = {
 +static struct clk dpll4_m3_ck = {
        .name           = "dpll4_m3_ck",
        .ops            = &clkops_null,
        .parent         = &dpll4_ck,
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 -      .clksel         = div16_dpll4_clksel,
 -      .clkdm_name     = "dpll4_clkdm",
 -      .recalc         = &omap2_clksel_recalc,
 -};
 -
 -static struct clk dpll4_m3_ck_3630 __initdata = {
 -      .name           = "dpll4_m3_ck",
 -      .ops            = &clkops_null,
 -      .parent         = &dpll4_ck,
 -      .init           = &omap2_init_clksel_parent,
 -      .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 -      .clksel_mask    = OMAP3630_CLKSEL_TV_MASK,
 -      .clksel         = div32_dpll4_clksel,
 +      .clksel         = dpll4_clksel,
        .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
  };
@@@ -767,12 -799,12 +767,12 @@@ static struct clk dpll4_m3x2_ck = 
  };
  
  static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate omap_54m_alt_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
@@@ -793,12 -825,12 +793,12 @@@ static struct clk omap_54m_fck = 
  };
  
  static const struct clksel_rate omap_48m_cm96m_rates[] = {
 -      { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate omap_48m_alt_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
@@@ -826,15 -858,31 +826,15 @@@ static struct clk omap_12m_fck = 
        .recalc         = &omap_fixed_divisor_recalc,
  };
  
 -/* This virstual clock is the source for dpll4_m4x2_ck */
 -static struct clk dpll4_m4_ck;
 -
 -static struct clk dpll4_m4_ck_34xx __initdata = {
 +/* This virtual clock is the source for dpll4_m4x2_ck */
 +static struct clk dpll4_m4_ck = {
        .name           = "dpll4_m4_ck",
        .ops            = &clkops_null,
        .parent         = &dpll4_ck,
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 -      .clksel         = div16_dpll4_clksel,
 -      .clkdm_name     = "dpll4_clkdm",
 -      .recalc         = &omap2_clksel_recalc,
 -      .set_rate       = &omap2_clksel_set_rate,
 -      .round_rate     = &omap2_clksel_round_rate,
 -};
 -
 -static struct clk dpll4_m4_ck_3630 __initdata = {
 -      .name           = "dpll4_m4_ck",
 -      .ops            = &clkops_null,
 -      .parent         = &dpll4_ck,
 -      .init           = &omap2_init_clksel_parent,
 -      .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 -      .clksel_mask    = OMAP3630_CLKSEL_DSS1_MASK,
 -      .clksel         = div32_dpll4_clksel,
 +      .clksel         = dpll4_clksel,
        .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
        .set_rate       = &omap2_clksel_set_rate,
@@@ -854,14 -902,30 +854,14 @@@ static struct clk dpll4_m4x2_ck = 
  };
  
  /* This virtual clock is the source for dpll4_m5x2_ck */
 -static struct clk dpll4_m5_ck;
 -
 -static struct clk dpll4_m5_ck_34xx __initdata = {
 +static struct clk dpll4_m5_ck = {
        .name           = "dpll4_m5_ck",
        .ops            = &clkops_null,
        .parent         = &dpll4_ck,
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 -      .clksel         = div16_dpll4_clksel,
 -      .clkdm_name     = "dpll4_clkdm",
 -      .set_rate       = &omap2_clksel_set_rate,
 -      .round_rate     = &omap2_clksel_round_rate,
 -      .recalc         = &omap2_clksel_recalc,
 -};
 -
 -static struct clk dpll4_m5_ck_3630 __initdata = {
 -      .name           = "dpll4_m5_ck",
 -      .ops            = &clkops_null,
 -      .parent         = &dpll4_ck,
 -      .init           = &omap2_init_clksel_parent,
 -      .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 -      .clksel_mask    = OMAP3630_CLKSEL_CAM_MASK,
 -      .clksel         = div32_dpll4_clksel,
 +      .clksel         = dpll4_clksel,
        .clkdm_name     = "dpll4_clkdm",
        .set_rate       = &omap2_clksel_set_rate,
        .round_rate     = &omap2_clksel_round_rate,
@@@ -881,14 -945,28 +881,14 @@@ static struct clk dpll4_m5x2_ck = 
  };
  
  /* This virtual clock is the source for dpll4_m6x2_ck */
 -static struct clk dpll4_m6_ck;
 -
 -static struct clk dpll4_m6_ck_34xx __initdata = {
 +static struct clk dpll4_m6_ck = {
        .name           = "dpll4_m6_ck",
        .ops            = &clkops_null,
        .parent         = &dpll4_ck,
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 -      .clksel         = div16_dpll4_clksel,
 -      .clkdm_name     = "dpll4_clkdm",
 -      .recalc         = &omap2_clksel_recalc,
 -};
 -
 -static struct clk dpll4_m6_ck_3630 __initdata = {
 -      .name           = "dpll4_m6_ck",
 -      .ops            = &clkops_null,
 -      .parent         = &dpll4_ck,
 -      .init           = &omap2_init_clksel_parent,
 -      .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 -      .clksel_mask    = OMAP3630_DIV_DPLL4_MASK,
 -      .clksel         = div32_dpll4_clksel,
 +      .clksel         = dpll4_clksel,
        .clkdm_name     = "dpll4_clkdm",
        .recalc         = &omap2_clksel_recalc,
  };
@@@ -971,22 -1049,22 +971,22 @@@ static struct clk dpll5_m2_ck = 
  /* CM EXTERNAL CLOCK OUTPUTS */
  
  static const struct clksel_rate clkout2_src_core_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate clkout2_src_sys_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate clkout2_src_96m_rates[] = {
 -      { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate clkout2_src_54m_rates[] = {
 -      { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
@@@ -1012,11 -1090,11 +1012,11 @@@ static struct clk clkout2_src_ck = 
  };
  
  static const struct clksel_rate sys_clkout2_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 2, .val = 1, .flags = RATE_IN_343X },
 -      { .div = 4, .val = 2, .flags = RATE_IN_343X },
 -      { .div = 8, .val = 3, .flags = RATE_IN_343X },
 -      { .div = 16, .val = 4, .flags = RATE_IN_343X },
 +      { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 +      { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
 +      { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
 +      { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
 +      { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
@@@ -1033,8 -1111,6 +1033,8 @@@ static struct clk sys_clkout2 = 
        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
        .clksel         = sys_clkout2_clksel,
        .recalc         = &omap2_clksel_recalc,
 +      .round_rate     = &omap2_clksel_round_rate,
 +      .set_rate       = &omap2_clksel_set_rate
  };
  
  /* CM OUTPUT CLOCKS */
@@@ -1049,9 -1125,9 +1049,9 @@@ static struct clk corex2_fck = 
  /* DPLL power domain clock controls */
  
  static const struct clksel_rate div4_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 2, .val = 2, .flags = RATE_IN_343X },
 -      { .div = 4, .val = 4, .flags = RATE_IN_343X },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 +      { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 +      { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
@@@ -1085,8 -1161,8 +1085,8 @@@ static struct clk mpu_ck = 
  
  /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
  static const struct clksel_rate arm_fck_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 2, .val = 1, .flags = RATE_IN_343X },
 +      { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 +      { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
@@@ -1257,25 -1333,25 +1257,25 @@@ static struct clk gfx_cg2_ck = 
  
  static const struct clksel_rate sgx_core_rates[] = {
        { .div = 2, .val = 5, .flags = RATE_IN_36XX },
 -      { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 4, .val = 1, .flags = RATE_IN_343X },
 -      { .div = 6, .val = 2, .flags = RATE_IN_343X },
 +      { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
 +      { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
 +      { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
  static const struct clksel_rate sgx_192m_rates[] = {
 -      { .div = 1,  .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE },
 +      { .div = 1,  .val = 4, .flags = RATE_IN_36XX },
        { .div = 0 },
  };
  
  static const struct clksel_rate sgx_corex2_rates[] = {
 -      { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE },
 +      { .div = 3, .val = 6, .flags = RATE_IN_36XX },
        { .div = 5, .val = 7, .flags = RATE_IN_36XX },
        { .div = 0 },
  };
  
  static const struct clksel_rate sgx_96m_rates[] = {
 -      { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
@@@ -1500,12 -1576,12 +1500,12 @@@ static struct clk i2c1_fck = 
   * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
   */
  static const struct clksel_rate common_mcbsp_96m_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
  static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
@@@ -1638,12 -1714,12 +1638,12 @@@ static struct clk hdq_fck = 
  /* DPLL3-derived clock */
  
  static const struct clksel_rate ssi_ssr_corex2_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 2, .val = 2, .flags = RATE_IN_343X },
 -      { .div = 3, .val = 3, .flags = RATE_IN_343X },
 -      { .div = 4, .val = 4, .flags = RATE_IN_343X },
 -      { .div = 6, .val = 6, .flags = RATE_IN_343X },
 -      { .div = 8, .val = 8, .flags = RATE_IN_343X },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 +      { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 +      { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 +      { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 +      { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 +      { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
        { .div = 0 }
  };
  
@@@ -2277,18 -2353,18 +2277,18 @@@ static struct clk usbhost_ick = 
  /* WKUP */
  
  static const struct clksel_rate usim_96m_rates[] = {
 -      { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 4,  .val = 4, .flags = RATE_IN_343X },
 -      { .div = 8,  .val = 5, .flags = RATE_IN_343X },
 -      { .div = 10, .val = 6, .flags = RATE_IN_343X },
 +      { .div = 2,  .val = 3, .flags = RATE_IN_3XXX },
 +      { .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
 +      { .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
 +      { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
  static const struct clksel_rate usim_120m_rates[] = {
 -      { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
 -      { .div = 16, .val = 9,  .flags = RATE_IN_343X },
 -      { .div = 20, .val = 10, .flags = RATE_IN_343X },
 +      { .div = 4,  .val = 7,  .flags = RATE_IN_3XXX },
 +      { .div = 8,  .val = 8,  .flags = RATE_IN_3XXX },
 +      { .div = 16, .val = 9,  .flags = RATE_IN_3XXX },
 +      { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
@@@ -2875,22 -2951,22 +2875,22 @@@ static struct clk mcbsp4_fck = 
  /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
  
  static const struct clksel_rate emu_src_sys_rates[] = {
 -      { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
  static const struct clksel_rate emu_src_core_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
  static const struct clksel_rate emu_src_per_rates[] = {
 -      { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
  static const struct clksel_rate emu_src_mpu_rates[] = {
 -      { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 +      { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
@@@ -2919,10 -2995,10 +2919,10 @@@ static struct clk emu_src_ck = 
  };
  
  static const struct clksel_rate pclk_emu_rates[] = {
 -      { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 3, .val = 3, .flags = RATE_IN_343X },
 -      { .div = 4, .val = 4, .flags = RATE_IN_343X },
 -      { .div = 6, .val = 6, .flags = RATE_IN_343X },
 +      { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 +      { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 +      { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 +      { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
@@@ -2943,9 -3019,9 +2943,9 @@@ static struct clk pclk_fck = 
  };
  
  static const struct clksel_rate pclkx2_emu_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 2, .val = 2, .flags = RATE_IN_343X },
 -      { .div = 3, .val = 3, .flags = RATE_IN_343X },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 +      { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 +      { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
@@@ -2993,9 -3069,9 +2993,9 @@@ static struct clk traceclk_src_fck = 
  };
  
  static const struct clksel_rate traceclk_rates[] = {
 -      { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 -      { .div = 2, .val = 2, .flags = RATE_IN_343X },
 -      { .div = 4, .val = 4, .flags = RATE_IN_343X },
 +      { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 +      { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 +      { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
        { .div = 0 },
  };
  
@@@ -3284,7 -3360,7 +3284,7 @@@ static struct omap_clk omap3xxx_clks[] 
        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2 | CK_AM35XX),
        CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
        CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
-       CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
+       CLK("omap-sham",        "ick",  &sha12_ick,     CK_343X),
        CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
        CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_3XXX),
        CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_3XXX),
@@@ -3396,8 -3472,8 +3396,8 @@@
        CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
        CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
        CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
 -      CLK("davinci_emac",     "ick",          &emac_ick,      CK_AM35XX),
 -      CLK("davinci_emac",     "fck",          &emac_fck,      CK_AM35XX),
 +      CLK("davinci_emac",     "emac_clk",     &emac_ick,      CK_AM35XX),
 +      CLK("davinci_emac",     "phy_clk",      &emac_fck,      CK_AM35XX),
        CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
        CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
        CLK("musb_hdrc",        "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
@@@ -3412,8 -3488,14 +3412,8 @@@ int __init omap3xxx_clk_init(void
        struct omap_clk *c;
        u32 cpu_clkflg = CK_3XXX;
  
 -      if (cpu_is_omap3517()) {
 -              cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
 -              cpu_clkflg |= CK_3517;
 -      } else if (cpu_is_omap3505()) {
 -              cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
 -              cpu_clkflg |= CK_3505;
 -      } else if (cpu_is_omap34xx()) {
 -              cpu_mask = RATE_IN_343X;
 +      if (cpu_is_omap34xx()) {
 +              cpu_mask = RATE_IN_3XXX;
                cpu_clkflg |= CK_343X;
  
                /*
@@@ -3424,17 -3506,10 +3424,17 @@@
                        /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
                        cpu_clkflg |= CK_3430ES1;
                } else {
 -                      cpu_mask |= RATE_IN_3430ES2;
 +                      cpu_mask |= RATE_IN_3430ES2PLUS;
                        cpu_clkflg |= CK_3430ES2;
                }
 +      } else if (cpu_is_omap3517()) {
 +              cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
 +              cpu_clkflg |= CK_3517;
 +      } else if (cpu_is_omap3505()) {
 +              cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
 +              cpu_clkflg |= CK_3505;
        }
 +
        if (omap3_has_192mhz_clk())
                omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
  
@@@ -3445,7 -3520,14 +3445,7 @@@
                /*
                 * XXX This type of dynamic rewriting of the clock tree is
                 * deprecated and should be revised soon.
 -               */
 -              dpll4_m2_ck = dpll4_m2_ck_3630;
 -              dpll4_m3_ck = dpll4_m3_ck_3630;
 -              dpll4_m4_ck = dpll4_m4_ck_3630;
 -              dpll4_m5_ck = dpll4_m5_ck_3630;
 -              dpll4_m6_ck = dpll4_m6_ck_3630;
 -
 -              /*
 +               *
                 * For 3630: override clkops_omap2_dflt_wait for the
                 * clocks affected from PWRDN reset Limitation
                 */
@@@ -3461,12 -3543,18 +3461,12 @@@
                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
                dpll4_m6x2_ck.ops =
                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
 -      } else {
 -              /*
 -               * XXX This type of dynamic rewriting of the clock tree is
 -               * deprecated and should be revised soon.
 -               */
 -              dpll4_m2_ck = dpll4_m2_ck_34xx;
 -              dpll4_m3_ck = dpll4_m3_ck_34xx;
 -              dpll4_m4_ck = dpll4_m4_ck_34xx;
 -              dpll4_m5_ck = dpll4_m5_ck_34xx;
 -              dpll4_m6_ck = dpll4_m6_ck_34xx;
        }
  
 +      /*
 +       * XXX This type of dynamic rewriting of the clock tree is
 +       * deprecated and should be revised soon.
 +       */
        if (cpu_is_omap3630())
                dpll4_dd = dpll4_dd_3630;
        else

diff --combined arch/arm/mach-omap2/devices.c
index 705a7a3,79dbf04..03e6c9e
--- 1/arch/arm/mach-omap2/devices.c
--- 2/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@@ -17,10 -17,8 +17,10 @@@
  #include <linux/clk.h>
  
  #include <mach/hardware.h>
 +#include <mach/irqs.h>
  #include <asm/mach-types.h>
  #include <asm/mach/map.h>
 +#include <asm/pmu.h>
  
  #include <plat/control.h>
  #include <plat/tc.h>
@@@ -28,6 -26,7 +28,7 @@@
  #include <plat/mux.h>
  #include <mach/gpio.h>
  #include <plat/mmc.h>
+ #include <plat/dma.h>
  
  #include "mux.h"
  
@@@ -455,39 -454,10 +456,41 @@@ static void omap_init_mcspi(void
  static inline void omap_init_mcspi(void) {}
  #endif
  
- #ifdef CONFIG_OMAP_SHA1_MD5
- static struct resource sha1_md5_resources[] = {
 +static struct resource omap2_pmu_resource = {
 +      .start  = 3,
 +      .end    = 3,
 +      .flags  = IORESOURCE_IRQ,
 +};
 +
 +static struct resource omap3_pmu_resource = {
 +      .start  = INT_34XX_BENCH_MPU_EMUL,
 +      .end    = INT_34XX_BENCH_MPU_EMUL,
 +      .flags  = IORESOURCE_IRQ,
 +};
 +
 +static struct platform_device omap_pmu_device = {
 +      .name           = "arm-pmu",
 +      .id             = ARM_PMU_DEVICE_CPU,
 +      .num_resources  = 1,
 +};
 +
 +static void omap_init_pmu(void)
 +{
 +      if (cpu_is_omap24xx())
 +              omap_pmu_device.resource = &omap2_pmu_resource;
 +      else if (cpu_is_omap34xx())
 +              omap_pmu_device.resource = &omap3_pmu_resource;
 +      else
 +              return;
 +
 +      platform_device_register(&omap_pmu_device);
 +}
 +
 +
+ #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
+ 
+ #ifdef CONFIG_ARCH_OMAP2
+ static struct resource omap2_sham_resources[] = {
        {
                .start  = OMAP24XX_SEC_SHA1MD5_BASE,
                .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
@@@ -498,20 -468,55 +501,55 @@@
                .flags  = IORESOURCE_IRQ,
        }
  };
+ static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
+ #else
+ #define omap2_sham_resources          NULL
+ #define omap2_sham_resources_sz               0
+ #endif
  
- static struct platform_device sha1_md5_device = {
-       .name           = "OMAP SHA1/MD5",
+ #ifdef CONFIG_ARCH_OMAP3
+ static struct resource omap3_sham_resources[] = {
+       {
+               .start  = OMAP34XX_SEC_SHA1MD5_BASE,
+               .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .start  = INT_34XX_SHA1MD52_IRQ,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .start  = OMAP34XX_DMA_SHA1MD5_RX,
+               .flags  = IORESOURCE_DMA,
+       }
+ };
+ static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
+ #else
+ #define omap3_sham_resources          NULL
+ #define omap3_sham_resources_sz               0
+ #endif
+ 
+ static struct platform_device sham_device = {
+       .name           = "omap-sham",
        .id             = -1,
-       .num_resources  = ARRAY_SIZE(sha1_md5_resources),
-       .resource       = sha1_md5_resources,
  };
  
- static void omap_init_sha1_md5(void)
+ static void omap_init_sham(void)
  {
-       platform_device_register(&sha1_md5_device);
+       if (cpu_is_omap24xx()) {
+               sham_device.resource = omap2_sham_resources;
+               sham_device.num_resources = omap2_sham_resources_sz;
+       } else if (cpu_is_omap34xx()) {
+               sham_device.resource = omap3_sham_resources;
+               sham_device.num_resources = omap3_sham_resources_sz;
+       } else {
+               pr_err("%s: platform not supported\n", __func__);
+               return;
+       }
+       platform_device_register(&sham_device);
  }
  #else
- static inline void omap_init_sha1_md5(void) { }
+ static inline void omap_init_sham(void) { }
  #endif
  
  /*-------------------------------------------------------------------------*/
@@@ -624,15 -629,6 +662,15 @@@ static inline void omap_hsmmc_reset(voi
  static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                        int controller_nr)
  {
 +      if ((mmc_controller->slots[0].switch_pin > 0) && \
 +              (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
 +              omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 +                                      OMAP_PIN_INPUT_PULLUP);
 +      if ((mmc_controller->slots[0].gpio_wp > 0) && \
 +              (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
 +              omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 +                                      OMAP_PIN_INPUT_PULLUP);
 +
        if (cpu_is_omap2420() && controller_nr == 0) {
                omap_cfg_reg(H18_24XX_MMC_CMD);
                omap_cfg_reg(H15_24XX_MMC_CLKI);
@@@ -828,33 -824,6 +866,33 @@@ static inline void omap_hdq_init(void
  static inline void omap_hdq_init(void) {}
  #endif
  
 +/*---------------------------------------------------------------------------*/
 +
 +#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
 +      defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
 +#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
 +static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
 +};
 +#else
 +static struct resource omap_vout_resource[2] = {
 +};
 +#endif
 +
 +static struct platform_device omap_vout_device = {
 +      .name           = "omap_vout",
 +      .num_resources  = ARRAY_SIZE(omap_vout_resource),
 +      .resource       = &omap_vout_resource[0],
 +      .id             = -1,
 +};
 +static void omap_init_vout(void)
 +{
 +      if (platform_device_register(&omap_vout_device) < 0)
 +              printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
 +}
 +#else
 +static inline void omap_init_vout(void) {}
 +#endif
 +
  /*-------------------------------------------------------------------------*/
  
  static int __init omap2_init_devices(void)
@@@ -866,11 -835,9 +904,11 @@@
        omap_init_camera();
        omap_init_mbox();
        omap_init_mcspi();
 +      omap_init_pmu();
        omap_hdq_init();
        omap_init_sti();
-       omap_init_sha1_md5();
+       omap_init_sham();
 +      omap_init_vout();
  
        return 0;
  }