Convert CONFIG_DEEP_SLEEP to Kconfig
authorTom Rini <trini@konsulko.com>
Thu, 24 Mar 2022 21:17:58 +0000 (17:17 -0400)
committerTom Rini <trini@konsulko.com>
Fri, 1 Apr 2022 14:28:47 +0000 (10:28 -0400)
This converts the following to Kconfig:
   CONFIG_DEEP_SLEEP

Signed-off-by: Tom Rini <trini@konsulko.com>
README
board/freescale/common/Kconfig
configs/ls1021aiot_qspi_defconfig
configs/ls1021aiot_sdcard_defconfig
include/configs/T102xRDB.h
include/configs/T104xRDB.h
include/configs/ls1021aqds.h
include/configs/ls1021atsn.h
include/configs/ls1021atwr.h

diff --git a/README b/README
index 3322f06..7c41f8d 100644 (file)
--- a/README
+++ b/README
@@ -403,10 +403,6 @@ The following options need to be configured:
                This CONFIG is defined when the CPC is configured as SRAM at the
                time of U-Boot entry and is required to be re-initialized.
 
-               CONFIG_DEEP_SLEEP
-               Indicates this SoC supports deep sleep feature. If deep sleep is
-               supported, core will start to execute uboot when wakes up.
-
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
index 300b01e..b41d93b 100644 (file)
@@ -22,6 +22,13 @@ config CMD_ESBC_VALIDATE
            esbc_validate - validate signature using RSA verification
            esbc_halt - put the core in spin loop (Secure Boot Only)
 
+config DEEP_SLEEP
+       bool "Enable SoC deep sleep feature"
+       default y if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
+       help
+         Indicates this SoC supports deep sleep feature. If deep sleep is
+         supported, core will start to execute uboot when wakes up.
+
 config FSL_USE_PCA9547_MUX
        bool "Enable PCA9547 I2C Mux on Freescale boards"
        help
index eac666d..b6e418c 100644 (file)
@@ -11,6 +11,7 @@ CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
+# CONFIG_DEEP_SLEEP is not set
 CONFIG_AHCI=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_OF_BOARD_SETUP=y
index 407b693..74043f6 100644 (file)
@@ -13,6 +13,7 @@ CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
+# CONFIG_DEEP_SLEEP is not set
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
index d9c72a8..5ecc897 100644 (file)
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
 
-/* support deep sleep */
-#ifdef CONFIG_ARCH_T1024
-#define CONFIG_DEEP_SLEEP
-#endif
-
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_PAD_TO              0x40000
index 562f7b3..76b0918 100644 (file)
@@ -70,9 +70,6 @@
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
 
-/* support deep sleep */
-#define CONFIG_DEEP_SLEEP
-
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
 #endif
index 773cc9b..dd37939 100644 (file)
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_DEEP_SLEEP
-
 #define CONFIG_SYS_INIT_RAM_ADDR       OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE       OCRAM_SIZE
 
index 3742203..2fb4c18 100644 (file)
@@ -6,8 +6,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_DEEP_SLEEP
-
 #define CONFIG_SYS_INIT_RAM_ADDR       OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE       OCRAM_SIZE
 
index b607dd3..cadcf22 100644 (file)
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_DEEP_SLEEP
-
 #define CONFIG_SYS_INIT_RAM_ADDR       OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE       OCRAM_SIZE