misc: k3_avs: Add OPP_LOW voltage and frequency to vd_data

J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance
Points as per (7.5 Operating Performance Points) section in the
Datasheet [0].
- A72SS/MSMC at 2 GHz/1GHz operation must use OPP_NOM.
- A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW
  voltage (though OPP_LOW voltage is recommended to reduce power
  consumption).

Add OPP_LOW frequency->voltage entry to vd_data.

The actual OPP voltage for the device is read from the efuse and
updated in k3_avs_probe().
OPP_NOM corresponds to OPP_1 and OPP_LOW to OPP_0 efuse register
fields, as described in the Datasheet [0]
The register offsets and fields are described in the TRM (5.2.6.1.5
WKUP_VTM_VD_OPPVID_j Register) [1].

[0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet)
[1]: https://www.ti.com/lit/pdf/spruiu1 (J7200 TRM)

Signed-off-by: Reid Tonking <reidt@ti.com>
Signed-off-by: Aniket Limaye <a-limaye@ti.com>

diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c
index 99a18a1..9d950d0 100644 (file)
--- a/drivers/misc/k3_avs.c
+++ b/drivers/misc/k3_avs.c
@@ -501,6 +501,10 @@ static struct vd_data j721e_vd_data[] = {
                .dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */
                .clk_id = 2, /* ARM clock */
                .opps = {
+                       [AM6_OPP_LOW] = {
+                               .volt = 0, /* voltage TBD after OPP fuse reading */
+                               .freq = 1000000000,
+                       },
                        [AM6_OPP_NOM] = {
                                .volt = 880000, /* TBD in DM */
                                .freq = 2000000000,

diff --git a/include/k3-avs.h b/include/k3-avs.h
index 1014d5d..f6f1031 100644 (file)
--- a/include/k3-avs.h
+++ b/include/k3-avs.h
@@ -20,6 +20,7 @@
 
 #define NUM_OPPS               4
 
+#define AM6_OPP_LOW            0
 #define AM6_OPP_NOM            1
 #define AM6_OPP_OD             2
 #define AM6_OPP_TURBO          3