mach-k3: am62ax: enable caches for the SPL stage
authorAnshul Dalal <anshuld@ti.com>
Thu, 22 May 2025 12:33:04 +0000 (18:03 +0530)
committerTom Rini <trini@konsulko.com>
Wed, 4 Jun 2025 18:27:57 +0000 (12:27 -0600)
board_init_f for the am62a is missing the call to spl_enable_cache which
exists for all other am62 platforms (check am625_init.c &
am62p5_init.c).

This allows the usage of caches while loading and parsing the u-boot.img
FIT resulting in ~2x speedup in the A53 SPL stage.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
arch/arm/mach-k3/am62ax/am62a7_init.c

index 28aee34..edd43a1 100644 (file)
@@ -191,6 +191,7 @@ void board_init_f(ulong dummy)
        if (ret)
                panic("DRAM init failed: %d\n", ret);
 #endif
+       spl_enable_cache();
 
        setup_qos();