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pata_sl82c105: wrong assumptions about compatible PIO modes
authorSergei Shtylyov <sshtylyov@ru.mvista.com>
Tue, 30 Jan 2007 17:40:30 +0000 (20:40 +0300)
committerJeff Garzik <jeff@garzik.org>
Fri, 9 Feb 2007 22:39:38 +0000 (17:39 -0500)
Fix the wrong "compatible" PIO mode choices: MWDMA0 has 480 ns cycle while PIO1
only has 383 ns cycle, and MWDMA2 timings matchs those of PIO4 exactly.

Signed-off-by: Jeff Garzik <jeff@garzik.org>
drivers/ata/pata_sl82c105.c patch | blob | history

diff --cc drivers/ata/pata_sl82c105.c
Simple merge
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