OMAP3 pwrdm: add CORE SAR handling (for USBTLL module)

34xx TRM Delta G->H notes that the CORE powerdomain has a hardware
save-and-restore (SAR) control bit for the USBTLL module, similar to
the USBHOST powerdomain SAR bit.  Split the existing core_34xx struct
powerdomain into two structs, one for ES1 and one for ES2, and add the
PWRDM_HAS_HDWR_SAR flag to the ES2 powerdomain.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --cc arch/arm/mach-omap2/powerdomains.h
Simple merge

diff --cc arch/arm/mach-omap2/powerdomains34xx.h
Simple merge