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drm/radeon: implement clock and power gating for CIK (v3)
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 23 Jul 2013 13:41:05 +0000 (09:41 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 30 Aug 2013 20:30:08 +0000 (16:30 -0400)
Only the APUs support power gating.

v2: disable cgcg for now
v3: workaround hw issue in mgcg

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

No differences found
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