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ARM: vexpress: introduce DCSCB support
authorNicolas Pitre <nicolas.pitre@linaro.org>
Thu, 3 May 2012 00:56:52 +0000 (20:56 -0400)
committerNicolas Pitre <nicolas.pitre@linaro.org>
Wed, 29 May 2013 19:50:34 +0000 (15:50 -0400)
This adds basic CPU and cluster reset controls on RTSM for the
A15x4-A7x4 model configuration using the Dual Cluster System
Configuration Block (DCSCB).

The cache coherency interconnect (CCI) is not handled yet.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>

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